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How the fuck do FPGAs actually work /g/?

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Thread replies: 13
Thread images: 3

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How the fuck do FPGAs actually work /g/?
>>
electronics and digital logic
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>>58321541
hmmm rlly maks u wonder...
>>
>>58321476
>>58321541
So... Magic?

Any cheap ones out there to play around with?
>>
File: 1421160684586.jpg (3MB, 3840x1200px) Image search: [Google]
1421160684586.jpg
3MB, 3840x1200px
>>58322785
icestick + icestorm tools is cheap and respects your freedoms

seriously not for the faint of heart though, also if you've never used an arduino it's not for you
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>>58322785

https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards

low level logic design for any complex problem will drive you insane
>>
>>58322785
>>>/g/csg
ALTERA FOGA Cyslonell is really cheap, on aliexpress for about $14, no idea how good it is though
Xilinx is more often than not a very safe bet but that'll cost you maybe $30

VHDL is the patrician choice and Verilog-cucks can just kys
>>
>>58323461
ripe
altera fpga cycloneII
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>>58323367
Pretty nice shit

thanks
>>
>>58323461
I know a guy that got burned trying to cheap out by using a shady Chinese supplier. I'd buy one and not expect to get anything.
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>>58323533
your on 4chan you don't have to pretend to know other people
>>
>>58321476
big grids of tiny pieces of logic with IO switchable between connections to a set selection other logic pieces.

you don't need to implement registers, SRAM caches, smallish-ish ALUs, etc. at the gate level, just figure out how to make more complex logic from these building blocks.

unfortunately it's not just discrete logic legos, there's a lot of analog signal timing and interference concerns that will keep your maximum achievable clock rates garbage if you don't understand and account for them.

the software that builds configuration bitfiles (turns Hardware Description Languages into actual routing/logic configurations) takes fucking forever, as do validation simulations. Shit like this is why incremental dev turnaround times are horrendous compared to software.
>>
>>58323732
Yes, it's bad, but while you might maybe one day do an ASIC, at least you'll have had FPGAs to get you prepared first. You'll never know how bad ULAs were by comparison..

At least you don't have to actually fab new mask layers every single time.
Thread posts: 13
Thread images: 3


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