Some Verilog

So, you want to draw out the state diagram and all the transitions, then at each posedge of the clock, you simply switch states, according to the logic in your state table. Here's an example from a past lab I did:

//SW[0] reset when 0
//SW[1] input signal

//KEY[0] clock signal

//LEDR[3:0] displays current state
//LEDR[9] displays output

module Lab5Part1(SW, KEY, LEDR);
input [9:0] SW;
input [3:0] KEY;
output [9:0] LEDR;

wire w, clock, resetn, out_light;

reg [3:0] y_Q, Y_D; // y_Q represents current state, Y_D represents next state

localparam A = 4'b0000, B = 4'b0001, C = 4'b0010, D = 4'b0011, E = 4'b0100, F = 4'b0101, G = 4'b0110;

assign w = SW[1];
assign clock = ~KEY[0];
assign resetn = SW[0];

//State table
//The state table should only contain the logic for state transitions
//Do not mix in any output logic. The output logic should be handled separately.
//This will make it easier to read, modify and debug the code.
always@(*)
begin: state_table
case (y_Q)
A: begin
if (!w) Y_D <= A;
else Y_D <= B;
end
B: begin
if(!w) Y_D <= A;
else Y_D <= C;
end
C: Y_D = (!w) ? E : D;
D: Y_D = (!w) ? E : F;
E: Y_D = (!w) ? A : G;
F: Y_D = (!w) ? E : F;
G: Y_D = (!w) ? A : C;
default: Y_D = A;
endcase
end // state_table

// State Registers
always @(posedge clock)
begin: state_FFs
if(resetn == 1'b0)
y_Q <= A; // Should set reset state to state A
else
y_Q <= Y_D;
end // state_FFS

// Output logic
// Set out_light to 1 to turn on LED when in relevant states
assign out_light = ((y_Q == F ) | (y_Q == G));

assign LEDR[9] = out_light;
assign LEDR[3:0] = y_Q;
endmodule

I did do a state diagram but I'm not going to use it because it's way too big for this type of problem. It would be much easier to use behavioral logic to describe the system in a few lines as opposed to writing code for each state switch. I just don't understand how to have two different counters in the same always block that get triggered based on some inputs.

This is how I started but now I'm stuck

always @ (posedge test or posedge reset)
begin
if (btn0 == 0 & btn1 == 0)
selector <= 0;
count <= 0;
else if (btn0 == 1 & btn1 == 0)
selector <= 0;
count <= count +1;


else if (count < 5 & btn0 ==1 or btn1 == 1)
selector <= 1;
count <= count +1;
else if

>>228228
I think that you are running into the issue of trying to find a "nice programming" way of solving the problem, which I don't think there is. This is low level programming - its going to be ugly. My suggestion would be to go with the state diagram and translate that directly into verilog. It's going to be long but not that long (maybe like - 30 states?) I think that's the correct approach to these sorts of problems. Got me through the course fine.

>>228235
on second thought there should not be that many states if you create a very efficient FSM

Its not about getting through the course. It's about learning how to code properly and not like a 5 year old. If I got a job as an FPGA programmer and someone saw me code like this, they would laugh my ass out of the building.