Digital Logic Design Question: You are designing an adder for

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Digital Logic Design Question:
You are designing an adder for the blindingly fast 2-bit RePentium
Processor. The adder is built from two full adders such that the carry out of the first
adder is the carry in to the second adder, as shown in Figure 3.75. Your adder has
input and output registers and must complete the addition in one clock cycle. Each
full adder has the following propagation delays: 20 ps from C in to C out or to Sum
(S), 25 ps from A or B to C out , and 30 ps from A or B to S. The adder has a
contamination delay of 15 ps from C in to either output and 22 ps from A or B to
either output. Each flip-flop has a setup time of 30 ps, a hold time of 10 ps, a clock-
to-Q propagation delay of 35 ps, and a clock-to-Q contamination delay of 21 ps.

If there is no clock skew, what is the maximum operating frequency of the
circuit?

The answer is 9.09 GHZ, which I calculated must make Tc 110 ps.
My attempt, I made Tpcq=35 ps, Tpd= 2*20 ps and Tsetup= 30 ps, but that leaves me 5 ps short of the answer.

Any help would be appreciated