Old shit

>>375848043
That's so fucking neat

The only profit-making division of Sony last year was SCE, if PS2 won't be a huge success, Sony will most likely go bankrupt.

Unfortunately finding rumors is hard as they usually don't survive being forgotten for decades so all there's available is official info.

>>375848043
>CPU...................200-300MHz
>not using AMD K6-2 333MHz in 1998
It was already blacked by PC

>DVD
FAKE

>>375851168
cuckposting wasn't a thing in 1998 you miserable faggot

Sony today released the floodgates about its new console, including the whole specs. Here's what SCEA's Phil Harrison has to say.

Official name: Still not disclosed so there's still a chance that we'll get PlayStation 2000 like some magazines refer to it.
Release date: supposedly before March 2000 in Japan and fall 2000 for North America and Europe
DVD Movie Playback: Sony is still uncertain wether it will support playing DVD movies or if it'll use the DVDs solely as a storage for games.
Modem: Despite having PCMCIA, they couldn't confirm if it'll support modem right now, but stresses that it's obviously being considered.
Backwards compatibility: PSX2 will run PSX games, however that's it. Despite being considered during R&D, no image enhancement such as higher resolution image output will be done as Sony wants 100% compatibility.

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On September 11th, 2001, bombs planted by the US Government will cause buildings 1, 2, and 7 of the World Trade Center in New York to collapse.

>>375851168
No games

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>>375852583

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Microprocessor Report made an article about the PSX2's hardware that was presented by Sony and Toshiba at International Solid-State Circuits Conference and in short this is what they had to say.
Emotion Engine is based on MIPS III, but shares a lot of MIPS IV instructions on top of its own 107 128bit instructions.It has 16K instruction cache, 8K data cache and 16K scratchpad.
They estimate the launch price of the console to be around $400-$500 as only manufacturing the EE alone with its 10.5 million transistors on 240mm2 of 0.25-micron silicon could cost $130 to build, according to the MDR Cost Model. With 42.7 million transistors on 279 mm2 the GS will also cost about $130 (assuming DRAM redundancy is used to improve yield). After shrinking to 0.18 micron process the price could be around $65 instead, allowing the $299 price point.
The 300-MHz EE packs a floating-point punch of 6.2 GFLOPS, three times that of Intel’s top-of-the-line 500-MHz Pentium III with SSE and 15 times that of a Celeron-400 (which lacks SSE).
Backwards compatibility is achieved by including the PlayStation CPU, which will be utilized as I/O processor while playing PSX2 games.
Although the EE provides conventional polygon-based rendering, it also supports more computationally complex curved surfaces, using NURBS-based (nonuniform rational B-splines) models, significantly boosting image quality.
EE has several autonomous units, VPU0 used to aid game code, physics simulation etc, while VPU1 is used for geometry, lighting etc. Image Processing Unit (IPU) and DMA controller is also present.

continued...

>>375854276
That comment was about a situation reported in 1999 you dweeb.

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>>375854392
Yeahh, my bad. Sorry. I guess I'm just retarded.
S-sorry.

I like reading about the different kind of rumors that existed about future consoles back then.

holy shit an actual good thread

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>in short
The core can issue two instructions each cycle and employs a simple in-order six-stage pipeline. Branch prediction is performed via a 64-entry branchtarget-address cache (BTAC), which records the target address of taken branches, and a branch-history table (BHT) integrated into the instruction cache (two bits per line). The BTAC is accessed in the first stage of the pipeline and, on a hit, provides a predicted target address on the next cycle. On a BTAC miss, the BHT, which is accessed in the instruction-fetch stage, is used to redirect instruction fetch, if necessary. Instructions are executed speculatively along the predicted path until the actual branch direction is resolved in the execute stage. If a branch is mispredicted, speculatively executed instruction results are discarded and the pipeline is restarted, imposing a three-cycle penalty.

VPU0 is directly attached to the core by a 128-bit operand bus, with each VPU0 macroinstruction executed as a MIPS coprocessor instruction. VPU0 macroinstructions are sequenced by microcode from a 4K SRAM instruction memory (microMEM0). The second vector unit, VPU1, runs asynchronously with the CPU, sequenced completely by microcode from its 16K instruction memory microMEM1). Each vector-unit microinstruction is a two-wide VLIW instruction. Each vector unit has thirty-two 128-bit floating-point registers, sixteen 16-bit integer registers, and a local data memory. The data memory for VPU0 (VUMEM0) is 4K in size, while VUMEM1 is 16K. Both VUMEMs can be read and written by the DMA controller.

>>375854837
Rumors reported by media are quite hard to find, especially nowadays.

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>>375852828

i haven't seen this leak of the ps5 before

I really suck at pointing out the relevant data, hopefully the E3 coverage will be much simpler. On the other had, you can at least get a complete image of PS2's inner workings.

The IPU can perform variable-length decoding, zigzag scanning, inverse quantization, and inverse discrete-cosine transform operations, decoding MPEG-2 macroblocks at a rate of 768 cycles per macroblock. After macroblock decoding, the IPU performs color-space conversion (YCbCr to RGB), vector quantization, and 4 x 4-ordered dithering. The IPU decompresses video at 150 Mpixels/s. In addition to its video-decoding duties, the IPU decompresses 3D-texture maps stored in main memory. The IPU performs on-demand texture decompression to either a high, medium, or low resolution, depending on the requirements of the image being rendered. The DMA controller transfers the decompressed video or texture data from the IFU’s output FIFO over the internal data bus to the GIF.

The internal data bus is 128 bits wide and operates at half of the CPU clock frequency. At a 300-MHz CPU speed, the bus provides a peak bandwidth of 2.4 GBytes/s. DMA transfers over this bus occur in packets of eight 128-bit words, minimizing the protocol overhead. The bus achieves an efficiency of about 85%, leaving an effective bandwidth of about 2 GBytes/s. The main-memory controller connects two channels of DRDRAM to the internal data bus. Although the two channels together can supply data at 3.2 GBytes/s, 33% faster than the internal bus can take it, buffering in the memory controller can make use of the extra bandwidth. I/O interface circuits on the EE connect the internal data bus to an external 32-bit I/O bus, which transfers data between the EE and the I/O processor (IOP) at 37.5 MHz. 150 MBytes/s of bandwidth is more than enough to carry all the I/O traffic from the DVD drive (1.5 MBytes/s), USB (up to 12 Mbits/s), IEEE-1394 (up to 400 Mbits/s), sound samples (up to 1.5 Mbytes/s), and a 56-Kbit/s V.90 modem.

It will sell like 40 million max.

I don't see the PlayStation follow up being anything but a medicore success.

The polygon display lists created by the EE’s vector units are transferred by the GIF to the GS over a dedicated 64-bit bus at 150 MHz. At this clock rate, the graphics bus provides 1.2 GBytes/s of display-list bandwidth, more than twice that of 2x AGP and more even than 4x AGP.
The GS provides a monstrous 48 GBytes/s of bandwidth, 30 times more than is provided by the discrete 128-bit 200-MHz SGRAM video memory used on many high-end graphics systems today. The GS’s 4M of embedded multiport DRAM has a databus width of 2,560 bits, allowing simultaneous 1,024-bit video reads, 1,024-bit video writes, and 512-bit texture reads. The GS uses a 32-bit RGBa pixel format with a 32-bit Z value and supports the full gamut of rendering functions, including texture mapping, bump mapping, fogging, alpha blending, bi- and trilinear filtering, MIP mapping, antialiasing, and multipass rendering. The 4M memory is adequate to double buffer an NTSC frame with full 32-bit color and Z buffering. The graphics synthesizer output supports NTSC, PAL, DTV, and VESA (1,280 x 1,024 maximum) formats.
SCE boasts of a peak rendering rate of 75 Mpolygons/s and a pixel fill rate of 2.4 Gpixels/s for Gouraud-shaded, Z-buffered, and alphablended polygons. Adding texture cuts the fill rate in half to 1.2 Gpixels/s, or 25 million 48-pixel quadrilaterals per second. The PSX2 can also draw 19 million sprites/s (8 x 8 pixels) and 150 million particles/s (for smoke and spark effects). Voodoo3 from 3Dfx, for example, delivers 183 Mpixels/s, while Nvidia’s RIVA TNT2 achieves 350 Mpixels/s. By the time PSX2 ships in volume, Pentium III’s speed could increase by nearly 50%, to 733 MHz, and AGP will have gone from the 2x to the 4x level (1 GByte/s). But even if these speedups fall straight through to drawing rates, which they won’t, the PSX2 will still be 2–4x faster than the fastest PCs and many graphics workstations.


That should just about wrap up the MPR report, now up to the E3 1999.

Also, that should've been April 19, not March 3.

Sony lawyers show up at bleem! booth, requesting to stop running Gran Turismo. After being told to go away, citing their recent victory in court against Sony as justification to continue the display, fleet of lawyers with E3 staff show up at booth, telling David Herpolsheimer to stop displaying the emulator, claiming that they have injunction against displaying the emulator. E3 staff didn't see the injunction, but chose to take Sony's word for it. Herpolsheimer stopped running GT and instead ran a 3rd party game, as well as slapped stickers over screenshots of Gran Turismo used on their promotional flyers.

>>375852583
>prey is bioschlock in space
now I dont want it

I'm more excited about Nintendo's Project Dolphin, which supposedly is going to ditch cartridges, so Square is sure to drop PlayStation development entirely. Bye Sony, it's time to go back to producing MiniDiscs and laptops like you do best. Leave the consoles to the big guys, Nintendo and Sega.

>>375855860
>nerd shit