Why is the Von Neumann architecture the end all be all?

>>7944887
Harvard architecture

>Under pure von Neumann architecture the CPU can be either reading an instruction or reading/writing data from/to the memory. Both cannot occur at the same time since the instructions and data use the same bus system. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time,[1] even without a cache. A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway.

FPGAs with millions of vertical stacks instead of a single bus to the ram are in development. Neuromorphic computing is a thing.

A month or two back an anon asserted that Von Neumann and his friends intentionally withheld most of their ideas from the USA because they knew Americans were just as bad as everyone else. If he's here I'd like to hear more on this.

I suspect Von Neumann's nanomachines were intended as software that would run on a hardware implementation of his binary neural networks. What happened instead was the Americans took their design and scaled them to a ridiculous size, while keeping the single bus.

>>7944904
so what's the downside? if it were that great then we'd all be using it instead, right?

>>7944951
This

>>7944951
Well, when you have separate instructions and data memory, you can fill one up and still have room in the other.

As soon as you start having more than one kind of memory, things get more complicated. How do you load stuff into the instruction memory? Do you allocate it in the same way as the data memory? Do you keep your allocation table for instruction memory in the instruction memory or data memory?

Most real computers aren't, of course, simply Von Neumann architecture. They have various layers and types of cache, they have separate main memory and persistent storage, graphics memory, networking buffers, they have microcode, firmware, CMOS configuration storage, etc.

Von Neumann architecture is more of an abstraction presented to the application developer, a simple model of computation so they don't have to deal with all the complicated shit that's really going on, and the actual variation from system to system.

>>7944951
We're using one particular architecture, mainly for historical reasons. If you think about SoC, we're heading in the direction where we have millions of tiny processors. They can't move or replicate, but their programs and data are more localized, which means communication only occurs when communication is the goal. Currently we communicate entire programs during context switching, which is inefficient. Ideally we would design an architecture for a particular use case.

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>>7944887

It was the easiest at the time to manufacture. Harvard was good but required as >>7944904
so eloquently said the "circuit complexity" was not optimal.

>>7944887
Neuromorphic architectures will arise within a decade.

>>7945354
>Harvard was good but required as >>7944904
>so eloquently said the "circuit complexity" was not optimal.
The Harvard model, as implemented on the Mark I was actually cheaper because the instruction memory was just paper tape.
Unlike later computers that loaded paper tape data into RAM, the Mark I actually ran instructions from the tape itself.
You could create an infinite loop by joining one end of the paper tape to the other with scotch tape.

>>7944904
Very few CPUs are either pure Harvard or pure Von Neumann, but I work with AVRs which are pretty much as close to Harvard as you can get (not pure though, as there exists instructions to read data from instruction space).

So OP makes no sense, Von Neumann is not the only architecture out there, Harvard was there first ;-)

>>7944887
One of the major advantages of the neural network is its ability to do many things at once. With traditional computers, processing is sequential--one task, then the next, then the next, and so on. The idea of threading makes it appear to the human user that many things are happening at one time. For instance, the Netscape throbber is shooting meteors at the same time that the page is loading. However, this is only an appearance; processes are not actually happening simultaneously.

The artificial neural network is an inherently multiprocessor-friendly architecture. Without much modification, it goes beyond one or even two processors of the von Neumann architecture. The artificial neural network is designed from the onset to be parallel. Humans can listen to music at the same time they do their homework--at least, that's what we try to convince our parents in high school. With a massively parallel architecture, the neural network can accomplish a lot in less time. The tradeoff is that processors have to be specifically designed for the neural network.

>>7944887
There is Harvard. There is also super Harvard, known from DSP56300 and others. these have been rather successful in their niches.

While a CPU might be von Neuman externally it is often Harvard deep inside since there is separate Icache and Dcache.