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Logic Circuits

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Thread replies: 19
Thread images: 4

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What program/method is the best way to making logic circuits? I don't know what to use.
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>>7688598
In uni we used quartus
http://dl.altera.com/?edition=lite
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>>7688608
is there any other way? I don't really want to download that large of a program for this, we'd only be on logic circuits for the next few days
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>>7688598
I'd highly recommend JFLAP.
The software website looks like it's straight out of the 90s but the program itself is fantastic.
If it asks you to fill out a form, just leave everything blank and hit submit and it'll work without you having to give it any information.
>>
I'm going to use this thread to ask since it's related:

How is this: X1 ^ ( X2 v X3) a boolean expression and this: ((X1 ^ X2) v X'3) not a boolean expression?
>>
Logisim
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logic.ly
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>>7688768
How do you draw the first question? For some reason it's more confusing to me than questions with 3 inputs
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>>7688803
doing your homework...
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>>7688686
if you mean ((X1 ^ X2) v X3'), then they are both boolian expressions
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>>7688836
Then my book is wrong?
>>
What you use is partly a matter of taste. CircuitLab is pretty awesome, but it's not free. You can get a demo though.

Best bet for simple purposes: http://sourceforge.net/projects/qlogic/

Best bet if you want to get more complicated:
http://sourceforge.net/projects/circuit/
Logisim is pretty easy to use, and has lots of good features.

Other stuff....
http://sourceforge.net/projects/gatesim/ looks a bit fancier. I don't like the curvy lines.

I've been meaning to try KTechLab. It seems to be microcontroller based, but looks like it has logic as well.
http://sourceforge.net/projects/ktechlab/
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>>7688817
Thank you.

How does this one look

~A ∧ ~B ∨ C

am I retarded ?
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>>7688850
Nice, I will try each of them out, thank you
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>>7688598
I've used LT Spice (it's pretty lightweight and free)
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Falstad circuit simulator. In browser, no DL required and user friendly
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File: tegaki.png (7KB, 400x400px) Image search: [Google]
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>>7688803
>>
>>7688900
the question should probably have parenthesis somewhere. If they were around the not a and not b the you would use the and output to be a input for the or gate
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>>7688598
Verilog
Thread posts: 19
Thread images: 4


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