https://www.youtube.com/watch?v=Jbf fGyrkjMM Oh dear. http

He broke the NDA. It's not fair for the others youtubers.

>>61606300
Wait, two? Don't we know for ages already it's four?

Who the fuck wrote this article. Also OP confirmed for slow poke.

>>61606300
Four Dies – What Does This Mean?
AMD assures Der8auer that Threadripper uses only two of the four dies, meaning the extra pair are disabled. We’re able to divine that anyway, since Threadripper only has 64 PCIe lanes. In other words, two eight-core dies equals 64 PCIe lanes. Four such dies – at 32-core – would equal 128 PCIe lanes. So, why the extra (redundant) dies? One theory is that the Threadripper and Epyc chipsets use the same chips, which are later customised for their respective uses. If true, this would certainly simplify (and hence cheapen) the manufacturing process. It is even possible that Threadripper processors are a result of Epyc fabrication errors, though this seems unlikely.

Interesting.

RIP
Why is TR so expensive then when their EPYC 16core parts are less than 700 burger shekels? Was it the two socket configuration?

>>61606319
He literally said he was told by AMD that he was allowed to post the video. He didnt break anything.

>>61606349
nope, all 4 dies are 64 pcie lanes in total...

ryzen 7 = 16 ; 16 x 4 = 64

>>61607202
its actually 32 lanes per die, but some are reserved for the chipset so you can only play 24 or so.

>>61606886
someone got fired on amd probably

>>61606349
this is what amd does with ccx pretty much
with yields well above 80% they can throw binned dies at each direction and dont even care about the cost
imagine if they manage to make even bigger cores on 7nm while having that insane yield..intel will suicide at once

>>61607447
zen2 is 6 cores per ccx. probably mainstream ryzen will have 12c/24t and the next threadripper 24c/48t.

https://www.msi.com/Motherboard/X399-GAMING-PRO-CARBON-AC.html
No NDA for mobos.

>>61607447
that sums up my feelings on it, AMD can just keep pumping out a small 8 core die repeatedly and it fits into every fucking position on the market, starting with servers at 32c/64t, all the way down to a 4c/4t desktop chips, where as with Intel they don't have that modular flexibility.

Zen+ and Zen2 should be coming next year and it will be on the high performance node instead of this low power shit we have now, and Intel cannot compete with the IPC gains on Zen2 nor the extra clock-speed provided by the high-performance node. Logically, Intel would just try and make a similar approach to AMD's Infinity Fabric, but I doubt it will happen anytime soon.

I'm still on a SB-E 3930k (4.6ghz 24/7) that I've had for the past 4 years just waiting for TR before upgrading, going from 6 cores to 12 or 16 cores will be pretty neat.

>>61607475
provide proofs

How can anyone excuse the fact that the CPU is twice as large as it has to be because there are two dead dies in the package. What the fuck is AMD doing?

>>61609676
AMD is providing single socket for manufacturers and single standard for cooling solution.

>>61607202
>>61607251
For Ryzen it's 24 lanes, 4 reserved for the chipset, 4 for SSD/SATA/PCIe, and 16 available (e.g. as PCIe 16x1 or 8x2). The chipset gives another 8 (2.0) lanes and other I/O.

>>61607475
there is not a single evidence of that as it stands right now zen 2 will be a more mature zen and plus be bigger this is only what we know

we dont know how much bigger
we dont know how many more cores it will have
we basicly dont know nothing more
and given how amd was able to sandbag the whole industry about zen i will take every rumor with a grain of salt

>>61607251
no. The lines are flexible and not reserved for anything. In Dual/Quad die formation and for 2P systems you of course need most of them for IF. Zen is a SoC, it technically doesn't need a chipset. It's just that for pretty much all applications you want one since only having PCIe devices kinda sucks

File: amd 8.jpg (218KB, 910x1015px) Image search: [Google]

218KB, 910x1015px

NOOOOOOOOOOOOOOOOO

>>61610015
As you said the lines are flexible. onboard zepplin are 4ethernet controllers and 8 sata3 controllers as well as some other things.

But I think the problem is AM4 being compatible with bristol ridge and RR which is causing there to not be any use of those features. I'd personally like a board that exposes all of those sata lanes without having to use a pch, it's probably the amount of usb ports consumers need.

so they basically glued four pc cpus together? disgusting

>>61609729
well, no. It's a different socket as the server platform, and cooling solutions for servers will be different anyways.

My guess as to why they went wit 4 dies is that it was simply due to manpower shortages. Not having to design a new MCM and simply using defective Epyc MCMs (though i think yield of packaging should be rather high) probably allowed them to bring out another platform in a short timeframe. Also they bin CPUs even before dicing, so they're probably even using to scrap dies as spaceholders for threadripper.

Also having this big socket and package will probably make the board more futureproof. Remember that the chipset is connected by PCIe by now and just provides some I/O functionality. With that big package and high power budget they could bring out interesting products in to future for the same platform. Do they earn anything on mainboards anyways? I don't think so, if that's true this platform might see new products for a long time.

>>61609935
If it's bigger, that means either 6 or 8 cores per CCX, and having 8 cores per CCX AND higher IPC seems unlikely even with the 7nm process.

http://www.pcworld.com/article/3211409/computers/why-ryzen-threadripper-has-two-mysterious-chips.html

>>61609676
>muh itx meme
It's a fucking socket that goes on the inside of presumably a large workstation case. Who gives a shit, are you worried about the amuont of material used and the enviroment or something? Think of all the extra waste cause by having to make new production lines to produce what is a fairly low volume part.

>>61610136
tl;dr they're dummy chips they don't actually do anything and they don't actually have 16 extra cores.

>>61610082
it's probably possible, but none of the mainboard manufacturers thought it was a feature worth having? With the timepressure they were probably under and a feature like that being new with ryzen/zen in general they probably just cobbled some 08/15 mainboard designs together, stuck some LEDs on it for the fancy high end stuff and called it a day.

>>61610123
if its bigger cores it means they will offer the same amount but more fast cores in general and given how the node has a low set of speed at about 5ghz (as per ibm) amd doesnt have to scale up the number of cores what so ever

>>61609676
How can anyone excuse the fact that Intel do the exact same thing? Their "HEDT" chips are just Xeons with disabled cores and an overclock.

>>61610152
>tl;dr they're dummy chips they don't actually do anything and they don't actually have 16 extra cores.
Dummy capacitors as well? Very skeptical.

File: mitx threadripper.jpg (114KB, 492x483px) Image search: [Google]

114KB, 492x483px

>>61610146
I hate and love that I have to post this in every thread.

>>61610152
no one knows pcworld took what dr said and just concluded something out of their ass

currently as dr said they are disabled cores
now if disabled means via software this is good news
if they are in hardware level aka the capacitors we saw missing then its a big harder but not impossible

>>61610171
>doesn't have to
but it might be useful. It will get more powerefficient, so they could cram more cores into their server parts, which would make them even more competitive.

And having a 6 core CCX would probably be useful for APUs.

>>61610219
Cores are already extremely efficient.
They need to lower uncore power draw.

>>61610198
those SMD parts are like 0.0012$ each, it makes no sense to use a different MCM package if you're using two dead/disabled/spaceholder/whatever dies anyways.

>>61606300
UNLOCK TIME MOTHERFUCKERS
Get your pencils ready!

>>61610246
true, but more cores is still useful for the server market. Especially if they stick to 1 and 2P systems

File: lol.gif (2MB, 200x150px) Image search: [Google]

2MB, 200x150px

>>61610210
HAHAHAHAHAHAHAHAHAHA
>amdfags will defend this

>>61610277
4S+ is dying and FAST.

>>61610169
AM4 has just been a safe play I think. The possibilities of what even a single zepplin die alone can do is incredible.

They could expose all 28(+4 chipset) lanes on the motherboard and with 8 cores completely shut down the only advantage the 7800 and 7820 have over ryzen.

Or a mini server that doesn't need a chipset with 8sata, 2x10gbe and 5 pcie 4x for nvme, gpus or controller cards running <30w with 2-8cores.

>>61610286
It's a photoshop for lulz you stupid braindead intelshill.

>>61610219
i can see such a move on hedt and server market only which will make sense

as it stands right now their mainstream offer is a 6c bringing the 8c down a bracket and make the current 8c a 10c it will be a fucking waste of everything cause there will be NOTHING and i mean NOTHING that will benefit
on the other hand if they provide faster cores with bigger caches all around (lets say 4mb bump on l3 and 2mb bump on l2) this will make a bigger difference than more cores

>>61610307
>bigger cachez
Means moar latency.

>>61610286
Why would I buy a chip that supports 64 PCIE lanes and only use 16 of them?

>>61610324
assuming that the current latench is going down the drain on zen 2 (as per amd ofc) adding more cache isnt really a bad move

>>61607202
Then how is Epyc 128 lanes?

>>61610210
Oh wow you know I thought you were trolling but I googled it and it is indeed that big.

Not that I give a fuck but that does look a bit silly.

>>61606300
at some point ill drop $$$ on the 1950x, aio, 399, and 32 more gb of ram, only to keep on playing vns and watch shows.

living the dream

>>61610355
No, i literally mean bigger cachez = moar latency.
It killed Bulldozer.

>>61610305
It isn't a photoshop you mong

>>61610376
to be fair, bulldozer was killed by a lot of things. But yes, latency scales almost linear with cache size. That's the main reason why we got 3 and in some cases 4 levels of cache to begin with

>>61610376
bulldozer got killed in many ways afterall i mean 2mb of cache isnt really an insane number its not like i suggest having a l2 of 20 mb and a l3 of 60 mb

>>61610307
Contrary to intel's lies, what amd releases on the desktop for ryzen is just left overs from epyc. If their servers want a 6core ccx, then the desktop is going to end up with 12core top end and everything else will filter down.

If the same 6core ccx goes into apus is another thing though, 4core ccx in rr2 means more room for delicious gpu cores and on the other hand intel's 6cores will have their igpu.

>>61610258
>c-cheap epycs?

>>61610292
yeah, it would open some neat things to do. I wonder if we'll see boards like that. It would be interested to know if they're even allowed to do so by AMD. If it's allowed according to AMDs design guidelines i figure we'll see something like that sooner or later. The processor and socket itself certainly should be capable of it.

>>61610421
Where's the source for it then? I'm calling BS on it as there's no chipset and no sata.

>>61610307
6 core CPU with a single enabled CCX would be pretty nice, though.

>>61610478
and then on IF and no IF means no free "oc" from faster RAM
kinda fucks up the whole reason of ryzen being as fast as it is now

>>61606352
because 8 core dies are worth much more than 4 core ones

TR might still be 2 dies, there's no telling until it's actually out

>>61610439
it's an interesting decision to judge how necessary IGPUs are in different price and performance categories. A 6 core probably doesn't really need on, especially if you offer your 4 (and less core) CPUs with one. On the other hand it's useful.

Another thing to consider is if AMD even wants to work on different CCX designs at the same time. With all the work they put into IF and what you heard from them in the last two years with where they plan to go with their semi custom stuff they might decide to just focus on a few designs and puzzle everything together out of them.

RR might be one of the last monolithic APU designs from them if everything works out acciording to the most optimistic guesses by some people

File: reijsgerij.jpg (103KB, 565x521px) Image search: [Google]

103KB, 565x521px

>>61610463
Just google image search "threadripper mini itx", you wont find that exact image but you'll find similar

>>61610503
>and then on IF and no IF means no free "oc" from faster RAM
No IF means lower core-to-core latency. Which means better performance than if you split the cores on two CCX regardless of how fast your RAM is.
Infinity fabric isn't what makes Zen FAST, it's what makes it SCALABLE.

>>61610503
RAM and IF OCing together provides a nice performance boost for the single fact that the IF is needed for cross CCX communication to begin with. A single CCX wouldn't be bottlenecked by that to begin with. But then again with that you'd be moving away from scalability, and sticking two RAM interfaces per CCX would be a waste (or we'd end up with server parts with hexdeca channel RAM lmao)

File: reijsgerij.jpg (465KB, 1296x972px) Image search: [Google]

465KB, 1296x972px

>>61610522
>>61610463
>>61610421
>>61610305
>>61610286
>>61610210
You know what I retract my statement, that is definitely a photoshop, and the picture I posted is clearly done in MS paint now that I look at it.

Here's a picture of an ATX x399 mobo, so the socket on those fakes is to scale, I'm just starting to think there will simply not be threadripper mini itx motherboards.

>>61610576
IF being tied to the ram speed is what makes it FAST also

>>61607202
retard and wrong

>>61610597
Asscock can always try.
Asscock will always try.

>>61606300
G L U E D T O G E T H E R
L
U
E
D

T
O
G
E
T
H
E
R

>>61610604
The bandwidth and latency within a single die is still going to be better than between dies.

File: 9081.gif (1MB, 288x288px) Image search: [Google]

1MB, 288x288px

>>61610614
>sockets will get so big that we'll see ITX boards with extension slots on both sides

>>61610516
It's the same decision intel has made as well. Right now their 6cores and up don't have an igpu. Forsee amd getting a 6core apu though, it's a big marketing thing to be able to say "six core laptop" even if it's almost useless.

As for multiple ccx designs is anyone's guess. I suspect dropping two cores from a 6core ccx isn't a great engineering feat in the grandscheme of things if IF is truely a decent fabric. But semi custom will probably never get that granular, the semi customers will get choice of 1-4 ccx + xGPU + memory interface + whatever else. But all from amd's predefined module, like lego.

>>61610597
>>61610614
Their newest idea was sodimms to save space, if they can get it running soc then there's hope. It's still fucking useless though.

>>61610657
indeed but then you gonna have to go the intel way and cut shit down which will add more complexity

>>61610657
not necessarily. Distance travelled is an almost insignificant part of latency when you get into the timeframe in which L3 cache or even RAM/DRAM operate. The by far biggest factor is the protocol and controllers over which you realize that inter die conncetion. More massive DQs means you need bigger driver transistors, more area means more interference and signal processing and so on

>>61606300
>>61606349
So how long until we can start unlocking extra cores phenom-style?

>>61606324
we've known for a long time that EPYC has four, everyone thought threadripper had only two

>>61610677
it wont happen anytime soon
a 6c laptop with an apu it will be a huge waste of resources that otherwise would have been wiser to use a discrete gpu

lets wait to see what jim keller did on the mobile zen power consumption and then we can speculate

>>61610729
Not saying it's a sensible idea, but it's something they at some point need to do to catch up to coffeelake and it's 6core laptop chips.

>>61607202
each CCX has 16 lanes, so 4x 2 CCX dies = 4*(2*16) = 128, desktop ryzen doesn't use all of them, and dual socket epyc uses 128 lanes as a socket interconnect (64 from each CPU)

>>61610677
yeah, but new designs and mascs need time. It takes like half a year to bring a chip from paper back into the labs to test if everything is working as intended, respins are expensive and take a shitload of time. The chips spend months in the factories until they're done. If you could just stitch new stuff together from prefabricated dies you'd drastically reduce cost and time to market. Just make it granular enough, if it's possible. It will probably never get to that point, but the thought is interesting. In the end most companies that want a semi custom deal worth a million plus bucks can probably live with another few months of added design time and the cost for a few masks.

>>61610720
sadly AMD found out how to physically disable binned parts units via lasercut. A shame

>>61610791
they just removed the specific capacitors anon

>>61607447
I love the fact that people talk about "yield" concerning the cpu making process. Like this manufacturing is a sort of alien technology even for the people who use it.

>>61610829
they are probably using dead chips as spacer anyways. But in chips with disabled cores per CCX they kill them via lasercut

>>61610831
but it is

>>61610771
There's no hard link to the ccs and pcie. In the zepplin everything is connected to the cross bar, that includes the 2 ccxs, 2x16io lanes, 2x memory controllers, two spare management io lanes, 4usb3, 3gmi links and probably some other gunk.

>>61610721
>>61610848
My only problem with this 2/4 chip thing, is could they have connected TR with all three xGMI links as it looks like there's only one link if it's a dead epyc chip.

>>61610874
>connected with three xGMI links
would've required a new package. Also i don't know how easy that would be to realize that and what benefits it would really have

File: DDf9gLCXUAAcRMW.jpg (9KB, 231x175px) Image search: [Google]

9KB, 231x175px

>>61610029
>intelfags into vore
>I7 eating radeon Graphics?
you cannot be this retarded surely

>>61606300
They're spacers, nothing to see here. They only remove the spacers if one of the dies are duds.