Intel Mesh, Does Overclocking it Fix Skylake-X?

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>>61455744
Comp. Arch Amateur hour w.r.t to design choices.
Dat lack of vision.

>>61455800
It's more like they designed it as a server arch first and a consumer arch second, similar to what AMD did with Zen. The difference is, Ryzen is comparatively inexpensive.

Skylake-X is not a gaming architecture
Skylake-X performing badly in the market its not targeting? Who cares

>>61456544
Skylake-X isn't a gaming architecture, and neither is threadripper, but threadripper is beating it in the gaming world and RAPING IT HARDCORE in the non-gaming arena.

>>61456544
1 month ago:
>Skylake-X will bring 5.0GHz on 6+ cores for gaming, it will absolutely destroy AMD, imagine a 7700k with double the cores?
Now:
>Skylake-X isn't a gaming architecture

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>>61456544
lmao.

>>61455853
Intel designed a high-end server chip, and it doesn't do desktop applications too well. I get some Itanium/Rambus vibes, in that intel chose something for big gains in the deep future.
AMD designed a workstation chip several notches below Intel's offering. Then they simply sell the same chip in 1, 2 or 4x configurations. It solves today's problems now.

>>61457160
>big gains in the deep future
When all the SKL-SPs will be on eBay aka totally irrelevant.

>>61457160
Just wait©

>>61457160
I think AMD is playing the long game.

Smaller chips are cheaper and have better yields, and we're finally moving to higher levels of parallelization.


AMD can cheaply make chips and shove em togther with infinity fabric, where intel did a half solution improving inter core communication while still keeping the dies large, making their chips expensive and hot.

>>61457528
I've already seen blubbering from the fanboy crowd that Intel will be doing MCM and it'll be a billion times better than Infinity Fabric and shoot rainbows out of your CPU's asshole etc.

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>>61457160
Keep telling yourself that, Shlomo.

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>>61457160
>Itanium/Rambus vibes
That is the exact opposite of what anyone wants to hear.

>>61457573
They will use EMIB to MCM something, but I doubt it will be any better than beefier and better IF in Zen2/Zen3.

>>61457657
When are the first EMIB CPUs hitting the market?

>>61457682
Dunno. Ask Intel.

>>61457573
Kinda like how they said intergrating the memory controller was a shit idea, until they did just that.


Eitherway AMD has a headstart (I have a feeling HBM gave them a leg up on this as well) and when intel catches up, amd can be another step ahead.

God bless competition, inovation galour.

>>61457720
>HBM
Yes-yes, it's the only TSV memory that survived for a reason.
Would work nice as on-package memory for future CPUs.

>>61457766
erm, I mean AMD's use of HBM gave them a leg up in designing a method to efficiently "glue" multiple chips together.


But I think if amd has a Zen APU with HBM.... They may have something intel cannot compete with no mater how hard they try.

>>61457795
TSV memory has nothing to do with engineering coherent interconnects.
In fact it was Magny-Cours that gave AMD a nice headstart for EPYC.

>>61457813
my response to that, is I'm just some tard on 4chan talking out of my ass.

yolo

>>61457795
Infinity Fabric is just Hyper Transport with a little polish. They had the tech they needed.

>>61457840
>little polish
I wouldn't call engineering custom on-package interconnects "little polish".

>>61457857
Consider it from this point, it just means that HT was that fucking good.

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What would it do for performance if AMD went full madman and put 1GB of HBM on package as L4 cache?

>>61458342
>1gb
Only 1gb?
8-hi stack is 8 gigs.
Also is requires faster IF and PHY on die.

>>61458342
eDRAM or HMC would really be a better choice for a L4 cache.

>>61458373
>eDRAM
Yes, but the capacity sucks.
>HMC
No.
Fuck no.

>>61458421
It's a fact that both have lower latency than HBM, they're simply better as a L4 cache.

You want bandwith, latency and low power draw for a cache, size is a plus, but it's not critically important.

>>61458491
Let's think of it more as of on-package memory than actual L4 cache.
Also HMC is shit.

>>61458373
Why not just another 128MB off-die SRAM ? Besides cost.

>>61458560
You can also stack it under the die, see Polaris.

>>61455744
>another CPU thread

>>61458589

I know Brian, /g/ isn't allowed to talk about cpus anymore since the Intel ones are a laughing stock and it offends you.

>>61458765
Delete this right now stupid goy.

>>61457840
Kurwa

>>61456591
I know, right?

It's almost as if those of us who tried to explain that the 7700k was an absolute dead-end for Intel because it simply wasn't going to be possible to get any more single-threaded performance on a four core without a new uarch, and thus inevitably Intel would be forced to throw away their clockspeed advantage in moving to 6+ cores knew what the fuck we were talking about.

Who would have thought?!

>>61459821
There's already idiots claiming Coffee Lake-S will hit Kaby Lake clockspeeds. The "muh clocks" ePeen jerkoff fest just never ends with Intel fanboys.

>>61459884

Clocks hadn't mattered for yhears until march 3rd 2017. When the 9590 was rocking 5ghz out of the box the trend was "lol clocks, only IPC matters!" (to be fair that is generally true) but now for some inexplicable reason its "if it can't clock really high its a failure of a cpu, IPC is irrelevant".

>>61457528
AMD isn't playing the long game;
AMD PLAYED the long game.

Their long con is now coming to fruition. They have the right architecture, the right process size, the right market acceptance of moarcoares, and the right technology to 'glue' it all together.

This is all the shit AMD's been building up for the better part of a decade finally coming together. I think the next gen Zen will be even better.

>>61458373
yeah, no

HBM has almost L3 cache speeds. Even just 2GB of that would increase performance on some workloads a lot

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>>61460243
The Zen die shrink could be amazing.

>>61460297
Latency.

>>61460297
BUT IT HAS GDDR LATENCY, MEANING IT'S STILL FASTER TO TALK TO THE LOWER LATENCY SYSTEM DRAM

IT'S NOT USEFUL AS A L4 CACHE