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Anonymous
Help i7 4790 3.6 GHz 2017-06-18 08:28:53 Post No. 60955551
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Help i7 4790 3.6 GHz 2017-06-18 08:28:53 Post No. 60955551
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Holly fuck guys. How does this work?
I want to load 3 arrays into memory, multiple 2 arrays with 3 nested loops and save the result in the third.
How is my data filling L1,L2 and L3 cache on Intel Haswell?
When I declare an array, does it load that entire array to cache or only that one memory line that it needs curently?
On start 3 memory 64b memory lines from 3 arrays for one operation in inner loop and the rest of cache is empty at this point. Is thi interpretation correct?
Is memory line copied in L1 automatically copied to L2 and L3? Or is it stored in L1 and only goes to L2 when it's evicted? (same for L2->L3).
What about TLB? After you miss the TLB address cpu looks for address in page table in RAM or asks L1 cache for data that might be there? What is the order?
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Wtf speak english
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>>60955576
On data load is CPU cache filled on all levels in Haswell or only L1 is filled and L2 gets populated only when data from L1 gets evicted?
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>>60955592
Seek medical help.
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>>60955576
How can you not understand? Every CS major should get it.
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>>60955600
No motherfucker, I must know.
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>http://www.agner.org/optimize/
Should have something about Haswell's cache design.
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>>60955600
>>60955576
please leave this board. this is a fucking actual technology thread for once and you act rude???
Fuck you fagman
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>>60955551
Did really nothing change in the pipeline betwwen Hsw and SB besides more registers?
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>>60955551
it just werks
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>>60955682
It doesn't. People on stack argue on how it works. Is L2 inclusive or exclusive? Is data always copied to L3 on every call?
Is TLB mapped physically or virtually?
Second level TLB is a direct fallback for L1 TLB, right?
If I use 4 k pages then they only translate addresses? Why do I need 1 mb pages then?
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>>60955747
You can't build a better cache system than Intel, if you can, show us.
Otherwise fuck off
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>>60955829
I don't know how it populates on Haswell architecture. Are you deaf?
/g/ used to be cool.
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>>60955843
It's not anyone's fault you fail to understand the best processors in the world.
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>>60955843
>/g/ used to be cool.
Yeh. When it was lolis getting literally split in half by futa cocks.
But /g/uro is /g/one
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>>60955867
>best
Haha.
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>>60955869
>>60955874
Can you please talk about CPUs?
Or are you underage children that don't know shit?
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Ok. A friend told me that data evicted from L1 goes to L2 and data evicted from L2 goes to L3.
What about the TLB though?
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>>60956332
Why don't you do your own research instead of expecting people to spoonfeed you? Try reading Intel's own documentation for starters. Sage.
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>>60956412
>Try reading Intel's own documentation
Fuck me am I right?
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>>60956489
are you dumb nigger? intel books on their arch are free
https://software.intel.com/en-us/articles/intel-sdm
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>>60955551
Just buy Ryzen.
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>>60957249
Daisuki desu, Amada
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