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Zen 7nm tapeout in 2017

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Thread images: 32

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Lisa Su confirms 7nm tapeouts scheduled for late 2017. Hopefully these are both Zen 2 and Navi. We should see a 7nm Zen 2 based Ryzen sometime in H1 2019.

https://seekingalpha.com/article/40...organ-technology-media-and-telecom-conference

Harlan Sur - JPMorgan:

>We talked initially in our discussion about the momentum carrying forward for the team and I think one of the things that you guys did a good job at Analyst Day was helping us to understand what’s next, right? And a good example of that is if we look at Zen 2, which you discussed at Analyst Day, that’s going to be ready sort of 2018, 2019 timeframe. Just maybe discuss in a little bit more granularity about the potential launch dates. These products are proposed to be using 7-nanometer technology from your foundry partners. When do you think such products are going to be sort of ready for tape-out and when do we see these products sort of out in the market?

Lisa Su:

>Yes, so our goal is to be very competitive in terms of our long-term roadmap. If you look at the foundry 7-nanometer roadmap compared to some of the other technologies out there, it’s actually really competitive. And I think the gap between sort of the foundry roadmap and like the Intel roadmap has gotten a lot closer. Our goal is to be aggressive with 7-nanometer technology. We will be doing tape-outs later this year. And as we get closer to production, we’ll give more insights there. But the idea is to be very competitive throughout the product portfolio.


Get your anuses ready.
There's a chance mobile APUs might roll out sooner since they're not getting the 14nm+ refresh like desktop chips are.
>>
>>60542477
bump
>>
Figured, should have started the thread with shitposting.
>>
Nice link pleb.
>>
>>60543104
https://seekingalpha.com/article/4075407-advanced-micro-devices-amd-presents-jpmorgan-technology-media-and-telecom-conference

Fucking truncating URLs
>>
>>60542477
>for 5 years we were on 28nm
>14nm is not even 2 years
i guess i'm waiting tm.
>>
>>60542477
Is it gonna be SOI or Finfet?
>>
bump for you op

vid unrelated
https://www.youtube.com/watch?v=YKTobOD1DEk
>>
>>60543216
FinFet by the looks; https://www.globalfoundries.com/technology-solutions/cmos/performance/7nm-finfet
>>
>>60542477
Meanwhile Intlel is struggling with 10nm.
>>
>>60543377
Cannonlake won't even be in desktops.
>>
>>60543398
7nm confirmed for 2022
>>
>>60543453
Intel will probably go straight to 5nm from 10nm
>>
>>60543509
In 2024
>>
>>60543509
>5nm
2026 then
>>
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>>60543377
NO
>>
Intel's 10nm is similar to 7nm from glofo/TSMC, but the most important thing is that Intel no longer has the 3 year advantage it used to have, so it can no longer piggyback purely on its fabs.
>>
>>60542477
Vega dead in the water then?
>>
>>60543550
Your post makes as much sense as your brain functions.
>>
2019 is way too late zen 2 better be ready by mid 2018 at the latest or based intel is going to wipe them the fuck out with cannon and coffee lake
>>
>>60543597
>wipe them the fuck out with a mobile only architecture and skylake

Must be nice to be retarded.
>>
>>60543609
>amdead rypoo 7 literally losing to four core intel processors
>intel bumping its mainstream lineup to six cores each by the end of the year

AMDone is bankrupt
>>
>>60543632
You tried.
>>
>>60543632
go away img_xxxx
>>
>>60543597
>based intel is going to wipe them the fuck out with cannon and coffee lake
10nm is slower than 14nm and desktop 10nm improvements are going to be terrible compared to Zen 2 improvements
>>60543632
lol the move to 6 core CPUs is a desperation mode on Intel's part. If they didn't the only thing they could do is RELEASE SKYLAKE AGAIN. At least this way they can pretend they have some forward momentum, even though they're at a dead stop.
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>>60542477
looks to me like AMD's fucking around with Phenom hexa and octacores paid dividends recently.

But I could be totally wrong and they were just a waste of time attributing nothing to Ryzen.
>>
>>60543744
It's due to Zen's CCX architecture they're able to be so flexible with core counts. Both in terms of scaling up and down.
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>>60543609
>>60543632
>>60543720
>BESIN FALLS
>mobile only architecture
>10nm is slower than 14nm
SHUT UP
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>>60543597
>>
>>60543632
>AMDone is bankrupt
>consoles still use amd
How can they be bankrupt if almost every console uses amd.
>>
>>60543870
They're paying console makers to use their shitty CPUs
>>
>>60543894
You mean like Intel did with laptop makers that resulted in a billion dollar fine they still haven't paid, and will be forced to soon just in time to subsidize ryzen chips in laptop for EU?
>>
>>60543894
>ps4 can play games in 60fps@4k using amd cpu/gpu
Yeah yeah amd is finished and dead.
>>
how fucked is Intel
>>
>>60544020
Aside from 10nm in a few years, they have nothing new to put out there other than their new architecture in 2020/2021.
>>
>>60543894
Yup they're losing money on each console sold OH WAIT https://venturebeat.com/2016/10/20/amd-reports-1-3-billion-in-q3-revenue-on-higher-console-chip-sales/
>>
Zen+ with 14nm+ and higher clocks in 2018
Zen2 with 7nm in 2019
Zen3 with 7nm+ in 2020
>>
Intel needs to really fix itself. AMD is destroying them right now. Mobile and desktop.

Intel, man, what happened to your company? You used to lead the way.
>>
>>60544020
Desktop? Retards would still buy their housefires. Datacenter? VERY fucked.
>>
>>60544127
Old jew Otellini left.
>>
>>60544127
They ignored their core market and tried everything to break into mobile. Didn't work. They should have had a new architecture ready to hit AMD down right as they were getting back on their feet. Instead they have nothing.
>>
>>60544079
there is no zen plus dumbass, zen 2 (pinnacle ridge) is due next year on 7nm and zen 3 is 7nm+
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>>60544256
There is Zen+, it's called Pinnacle Ridge and it's Q1 2018.
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>>60544256
>due next year on 7nm
>7nm
>next year
You sure about that?
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>>60544256
>seres no zen plus you shhstupid its zen 2 big difference
>>
>>60542477
The fact that Intel hasn't even gotten their 10 nm node into production yet says something about this "7 nm" node, I think.
>>
>>60544284
I can pretty much guess what it's gonna be.

Basically Ryzen at higher clocks(200-400MHz more) with 32 enabled PCIe lanes and bug fixes.
Hopefully they manage to gain some IPC as well from those bug fixes, but I figure that's reserved for Zen2 and 3.
I'll be glad if I get pleasantly surprised.
>>
>>60544365
What does it say?

>Based on FinFET transistor architecture and optical lithography, with EUV compatibility at key levels, the new 7nm FinFET technology is expected to deliver more than twice the logic and SRAM density and >30% performance boost compared to 14nm foundry FinFET offerings. This technology will be supported by a full platform of foundation and complex intellectual property (IP), including an application-specific integrated circuit (ASIC) offering.
Twice the density, it's a full node shrink like 28>14nm was
>>
>>60544380
>twice the logic and SRAM density
Area scaling you twit. If the feature length really went from 14 to 7 nm, the actual logic density would have quadrupled.
>>
Highly unlikely but it could be true.... I'm craving a budget apu build but using the am4 architecture
>>
>>60544415
Everyone knows marketing names like 10nm and 7nm are not fucking feature sizes since years ago.
>>
>>60544418
>Highly unlikely but it could be true....
What the fuck are you talking about?
>>
>>60542477
If we assume a late Q4'17 tape out we should also assume a late Q2'19 commercial release.

GloFo themselves even said volume production for 7nm likely won't be ready until the later part of 2018, at best.
>>
>>60544445
Having 7nm tapeouts in 2017
>>
>>60544363
14nm+ vs 7nm is not a small difference. Pinnacle Rigde is a Zen refresh not the 7nm Zen2
>>
>>60544418
>Highly unlikely but it could be true...
>literal AMD CEO says about 7nm tapeouts
Holy fucking shit please be bait.
>>
>>60544476
Lisa Su just fucking said tapeouts are happening in late 2017.
H1 2017 is nearly over, I'm pretty sure they're well aware when they can tapeout.
>>
>>60544433
Yes, well, if they have a 14 nm node, and double the logic density, then one might think that whatever the feature length is, it would scale with 1/√2, which would put it right at 10 nm.
>>
>>60544482
A design ES tape-out only tells us the general time frame for commercial release.

People seem to be assuming this means they have taped out a commercial production chip for testing, while I most assuredly tell you it's going to be 12-18 months minimum before we see or hear in detail about the product.
>>
>>60544453
>And a good example of that is if we look at Zen 2, which you discussed at Analyst Day, that’s going to be ready sort of 2018, 2019 timeframe.


In the OP.

2 years between retail and tapeout would be retarded, even retardedly huge 600mm2+ chips don't take that long, and we're talking about 200mm^2 or even smaller chips.
It would be no surprise if AMD can get chips out sooner, look at the Vega situation, they've got first dibs on 8GB HBM2 stacks, while Volta is still using 4GB ones, no one expected that.
>>
>>60544500
For comparison, Vega taped out in November 2016.
Less than 8 months before its release.
>>
>>60544515
volume ramp = several months until volume production has made enough stock for commercial sales

Glofo says late '18 volume ramp/production. This points to a mid/late 1H'19 time frame at best.

My point is that there's been no indication that 7nm will be ready that damn fast, and if it isn't then Zen2 isn't using it (yet), and if it is thern GloFo has been underselling themselves, which makes no sense
>>
>>60544542
You know you're arguing against Glofo's own press releases and Lisa Su's words, right?

I can bet my nuts there'll be limited availability of Zen2 in the form of Server/Laptop chips late 2018 with full production in Q1 2019, exactly a year after Zen+ in Q1 2018
>>
>>60544596
How does that not agree with what I said?

Allright, my time frame might be conservative instead of optimistic. An expected 2H (which means anything from July to December mind you) HVM start still means anything from January to March '19 availability.
>>
>>60544596
Does EUV actually do anything but make cost lower?
Any physical characteristics like smaller gate pitch?
>>
>>60544662
http://www.anandtech.com/show/10704/globalfoundries-updates-roadmap-7-nm-in-2h-2018
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>>60544284
no thats zen 2, zen + refers to anything after summit ridge

>>60544343
its taping out this year, fuck off intel fanboy

>>60544363
nice argument fag
>>
>>60542477
>7nm tapeouts scheduled for late 2017.
>ready sort of 2018/2019

Quite a large gap between tapeout and release, they'll probably stock up a decent number of smaller chips even before full production starts.

Perhaps Raven Ridge 2?
>>
>>60544662
The point with EUV is that it has shorter wavelength and thus greater resolution, which would lessen the reliance on tricks like double/triple patterning. I don't know enough to be specific, but apparently double/triple patterning is quite problematic to work with.
>>
>>60544813
I bet they taped out that early because they want to get server chips into customer hands for testing as soon as possible.
After tapeout, some basic debugging and cleanup for a few months and you got a working chip you can send out to partners and OEMs for compliance and perf testing.

Makes perfect sense, their server initiative is far more important than any other market.
>>
>>60544851
You know what? 7nm DUV uses QUAD patterning.
>>
>>60544813
If past 14nm cycle is indication they would do Vega 20 (Polaris successor?) with it first
>>
>>60544878
No, Vega20 is big juicy FP64 chip. Vega11 may or may not be Polaris successor.
>>
>>60544878
Vega 20 is a fp64 chip so it's a low volume part, they can get away with releasing it in 2018.
It's basically AMD's version of V100, cool tech but low volume.
>>
>>60544878
>>60544893
vega 20 was obviously scrapped in favor of navi
source: FAD roadmaps list 7nm only under navi and not vega
>>
>>60544910
There's certainly going to be Vega refresh. Vega20 may be on 14nm+.
>>
>>60544910
It could be on 14nm if they get better performance then expected.

These >>60544878 slides are pretty old.
>>
>>60544910
It would be even better if they pushed Navi up the schedule
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>>60544957
They are probably going to. Also what's Navi all about?
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>>60544975
Nobody knows, but the most famous speculation is multiple GPU dies on a MCM like Epyc
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>>60544975
Not much info aside from "Scalability" and "Next-Gen memory". Possibly referring to combining smaller dies with infinity fabric and GDDR6
>>
>>60544986
>Nobody knows, but the most famous speculation is multiple GPU dies on a MCM like Epyc
MCMed GPUs? That's pretty insane.
>>
>>60542477
>We should see a 7nm Zen 2 based Ryzen sometime in H1 2019.
It shouldn't take that long.
Ryzen was taped out in Q2(or Q3?) 2016 iirc.
Lisa said it usually takes 9 months from tapeout to market.
>>
>>60545018
You know Zen's B1 revision(what most known as F4 in the OPN code who remembers early leaks) came out in February, they only had a month to ramp up Ryzen and they still did it, thanks to the impressive yields.
>>
>>60544995
>That's pretty insane.
if it happens it's also going to be the most amazing achievement in GPU history due to the complexity of it.
>>
>>60545075
I don't see how, CPUs already do it, as pretty evidenced by chips even preceding threadripper/EPYC.

GPUs should be far more simple to glue together due to them being 80% simple ALU and not being so latency dependent like CPUs are.
>>
>>60545057
yup, I assume the 9 months thing accounts for validation and revisions
>>
>>60545075
>if it happens it's also going to be the most amazing achievement in GPU history due to the complexity of it.
It would also mean that
>pajeets > chinks
>>
>>60545165
There are 3000+ people working on AMD's GPUs and probably over double that working on nvidia GPUs, you're gonna have to provide me with the race and nationality of at least 51% of these people if you wanna make any claims like that.
>>
>>60545233
Autism.
>>
>>60545096
>I don't see how, CPUs already do it
because the cores are mostly independent, they're also better suited for handling inter chip communication and NUMA isn't too much of a problem with the DDR being lower latency than GDDR.
for GPUs you'd essentially need the command processor, ACEs and all the I/O to be on one die and only have the shader engines on separate dies. There's a lot of work needed to handle the synchronization and memory queues (especially with atomic ops).
>>
>>60545096
GPU on MCM seems far more difficult on the driver side than anything else.
>>
>>60543509
Optical interconnects? They tested that in 08/09
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>>60545165
They are all chinks
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>>60544284
Zen# naming is better than +/++ beyond 3
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>>60542477
>2020
dude, wait lmao
>>
>>60545325
And EUV deployment was originally planned for 2007, to be delayed over a DECADE.

Physics is scary, especially when you're limited by money.
>>
>>60545350
>>60545350
It's Raja and Chang at the top. Does AMD even hire pajeets?
>>
>>60545376
There was one in Zen design team. And Raja.
>>
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>>60543870
>switch
>>
>>60545350
>Shanghai

AMD's main R&D team is in Colorado IIRC
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>>60545376
Intel does.
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>>60545350
And the Zen design team.
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>>60545414
That's the team that designed EMIB aka the last competent guys in Intel.
>>
>>60545397
>not a console
>>
>>60542477
>intel having issues with 10nm
>AMD jumping straight to 7nm from 14

this should be good to watch
>>
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>>60545366
>he doesn't know how to read powerpoint slides
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>>60545376
https://www.youtube.com/watch?v=dPxV_2j5A2A#t=20m13s
White boy in the back drinking pop?
Vega
Chang
>>
>>60545428
Let's play, spot the jew.
>>
>>60545456
Intel's problem is that it has to juggle far more than just fabs, while keeping 60% margins, and keeping investors happy, while not losing face.

Difficult.

Meanwhile TSMC/Glofo only need to focus on fabs, Glofo gets IBM's foundry tech and it gives nice cash injection from Mubadala to help accelerate.

I'll just remind you that GloFo some years ago wasn't even considered a cutting edge fab, and now with 7nm it's uncomfortably close to Intel and TSMC
>>
>>60545479
The woman, or the guy next to the terrorist
>>
>>60545521
>I'll just remind you that GloFo some years ago wasn't even considered a cutting edge fab, and now with 7nm it's uncomfortably close to Intel and TSMC
IBM tech and stuff certainly helps a lot.
>>
>>60545543
IBM is only for their upcoming FD-SOI and 7nm.
Samsung was 14nm, but GloFo's own 28nm SHP was very impressive.

Either way, GloFo has established itself capable of competing with the giants.
If you told me this half a decade ago I would have spat in your face
>>
>>60543377
Daily reminder feature size has no relationship with marketing names
>>
>>60545350
>>60545428
on a scale of 0-10, how smart are the people in these pictures?
>>
>>60545982
Very smart in their field.
>>
>>60545350
at least they're not pajeets. though i do consider raja as a honorary chink.
>>60545534
that's not a terrorist. that's a based sikh
>>
>>60542477
>.png
Amazing how AMD caught up.
>>
>>60542477
lol I just realized that's a beema die shot in the background
>>
>>60542477

this is why I rather pay the intel & nvidia premium. at least I get future AMD performance NOW.
>>
>>60548205
Really? Let's see that 8 core 16 thread 65 watt $305 Intel CPU, then.
>in b4 muh clocks
>>
>>60548205
>MFW Threadripper BTFOs 2/3 of Intel's 1S Xeons for $999.
>>
>>60542477
Best case is product launch 9-12 months after tape out. Worst case is around 2 years. Hoping it's 9 months. At least for Zen. I want to get my hands on that sweet, sweet Zen 2 asap.
>>
>>60544284
That roadmap is dead. At their financial analyst day they said APUs are ahead of time (previous 2018, now 2H 2017) and on 14+. There's also no Vega shrink, but there will be Vega on APU on 14+.
>>
>>60545398
AMD's China team did Fiji and Polaris IIRC, and now Vega
>>
>>60548205
>intel premium
So you want to pay more for worse performance?
>>
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>Epyc
I will never get used to this stupid fucking name. It is somehow much harder to read than Epic and brings to mind the lamest possible marketing department.
>>
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>>60545414
It's Pajeets all the way down at good old Intel Aviv.
>>
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>>60543982
*30ish fps scaled to 4k
>>60544256
it's right there in op pic.
>Data is hard to interpret
14nm,14nm+, 7nm, 7nm+
>there is no zen+
>>
>>60549160
14nm+ is APUs in the 2nd half of 2017 bub
>>
>>60542477
>and Navi.
More like Vega 20 first.
>>
>>60549160
>Zen 3's timeline ENDS in 2020
>Zen 2 in 2019 guys!
Are you retarded?

It's pretty clear that Zen 3 is through 2019 to 2020. Which means Zen 2 is through 2018 to 2019.
>>
>>60549397
Can you imagine the devastation if 7nm Zen2 comes out next year?!?! With INCREASED clocks from IBM's 7nm process versus Intel's 10nm being slower than 14nm?!?!

HAHAHAHHAHAHAHA
>>
>>60549465

Given zen already has an IPC lead (that isn't particularly leveraged right now) such a chip would kick Intel right in the money making sectors hard.
>>
>>60543509
>5nm
the smallest copper gets is 7nm you fucking retards
>>
>>60550343
desu those measurements are mostly bullshit anyway at this point
like glofo/samsung/tsmc with 20nm + finfet = 14/16nm
wouldn't be surprised if they release 5nm which is just 7nm with EUV or something

but you're right, 7nm is the limit for current technology
>>
>>60551176
And where GloFo plans to go after "7nm+"?
>>
>>60551258
a different material from silicon. maybe carbon.
>>
>>60551805
graphene
>>
>>60552105
A meme.
>>
>>60544365
GloFo's 7nm FinFET is pretty much 14nm with FinFET transistors, which gives it something close to 7nm performance.
>>
>>60552105
Enjoy to pay 500k $$$ per core.
>>
>>60552253
So price of I15?
>>
>>60549491
>Given zen already has an IPC lead
Stop this meme already. Yes, Zen is capable of 5 instructions per clock vs. Intel's 4, but what matters is how the CPU can actually leverage that on real programs. By the same metric, Bulldozer had the same IPC as Intel.

In reality, there are some tests where Zen beats Intel in IPC, but it loses slightly in most.
>>
>>60552199
GloFo's 14 nm process already uses finfets, though. There's literally no way they even could be using planar transistors at 14 nm.
>>
>>60553120
GloFo's 14nm FinFET was closer to 20nm. Their 7nm FinFET is a node reduction from their 14nm FinFET, which means it will be in the neighborhood of 14nm.
>>
>>60553098
Please feel free to provide some evidence for your assertion.
>>
>>60545982
IQ 120+

but focused and possibly braindead in categories outside their area of expertise
>>
>>60551805
>>60552105
graphene is carbon, stupid
>>60551176
>for current technology

uhh no for physics it is the limit
>>
>>60553185
I know I could post any amount of benchmarks and it wouldn't really matter to /g/ anyway. I just presented the general impression I've gotten from seeing a large variety of benchmarks. As I said, there is no dearth of benchmarks where Zen wins in IPC, it just seems to be losing (if only slightly) in most.

I do wish I had a Ryzen system myself so that I could actually try out various workloads and see in what kinds of programs it wins vs. loses to Intel in terms of IPC. I'm almost considering building one just for the task.
>>
>>60553219
>for physics it is the limit
for silicon, yes it is the limit. not for others.
we have 1 nm transistor already and it is from carbon.

https://www.theverge.com/circuitbreaker/2016/10/6/13187820/one-nanometer-transistor-berkeley-lab-moores-law
>>
>>60553185
>1700X 4.5Ghz
How the fuck?
>>
>>60553373
liquid nitrogen and lot of voltage.
>>
>>60553315
I would actually like to see them to go look at their methodologies. You actually appear to not be shitposting so I have no interest in shouting at you about them.
>>
>>60553373

http://wccftech.com/amd-ryzen-1700x-benchmarks-leaked-beats-kaby-lake-ipc/
>>
>>60553391
I'm not at all trying to say that Zen has bad IPC, it's just that some retards have picked up Agner Fog's conclusion that Zen has higher maximum throughput that Intel does to mean that "Zen has higher IPC than Intel".

It is true that Zen has higher theoretical throughput, but that is irrelevant for real-world, practical IPC. By the same measure, Apple's Twister-and-later cores would be the fastest of all (I believe they have a max throughput of 6 or even more instructions per cycle).
>>
>>60553373
It's a normalized score, where they've effectively just multiplied some score by the factor of the real Ryzen frequency vs. an imagined 4.5 GHz Ryzen.

Which is really stupid, since increased core frequency does nothing to mitigate memory latencies. It is extremely common for IPC to actively decrease on the same processor when increases its clock frequency precisely because of this. Never ever trust such benchmarks.
>>
>>60553705
Actually the picture is more flattering to Intel with the scaled version. Here is the unscaled comparison from the same article.
>>
>>60553626
I'm not arguing with you, I'm just asking for some links to some of the IPC comparisons you've seen so I can read them.
>>
>>60553372
yep, so?
also for copper, dumbass... as was already said.
>>
>>60553390
>liquid nitrogen meme

my 1700X is at 4.1ghz and runs almost 62C under load.
>>
>>60553626
Let's look at this from another angle, the market has been using the same wide Intel core for many years, and that's unlikely to change for the desktop.

But what about server? They're not adverse at rewriting their code for specific uarches, and they can more than likely take advantage of Zen's 5 wide instruction per clock cycle.
>>
>>60553825
Is it a lot? I've been running FX-6350 on 85-90C at full load for over three years (yeah I'm an idiot, but I never got any big problems from throttling, maybe it's broken in my chip) and iirc Ryzen has higher Tjmax and higher AMD-suggested safe temperatures.
>>
>>60544957
I think vega is navi, the real vega already scrapped.
it possible upcoming vega is navi hybrid
>>
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>4.5ghz 7700k
>same as 2600k just OCed on smaller silicon
>nothing changed in 7~ years

Intel has done this many times in the past
They can make great chips again. But they need to be forced via competition to do that
>>
>>60553922
no.. it's very cold. which is why I called liquid nitrogen a meme
not needed
ryzen is impossible to hit tjmax before you destroy the chip with too high of voltage. It runs cold as fuck with """"correct""" cooling (aka stock or other heatsinks that aren't garbage like intel's)
>>
>>60553794
>I'm not arguing with you
Yeah, I know, I was just trying to clarify where I was coming from.

>I'm just asking for some links to some of the IPC comparisons you've seen so I can read them.
Not sure I have any good specific examples; as I said, it's just the general impression I've collected from all around the place. I don't even have a way back to some of the benchmarks I have in mind. But if only for the sake of science, perhaps, I found Anandtech's early tests to be fairly representative of the general trend:
http://www.anandtech.com/show/11170/the-amd-zen-and-ryzen-7-review-a-deep-dive-on-1800x-1700x-and-1700/17
In the single-threaded benchmarks, Ryzen tends to lose by slightly more than its cycle-time disadvantage (not in all though, of course).
>>
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>>60553098
It true, only retard use game for ipc test
>>
>>60548551
>Best case is product launch 9-12 months after tape out.

there's 0 chance of launch 12 months after tapeout. it generally takes 15 months minimum, often longer.
>>
>>60549491
>Given zen already has an IPC lead (that isn't particularly leveraged right now)

it doesn't, all superscalar cores have higher theoretical throughput than is possible in practice.
>>
>>60554112
So according to you, Vega should release somewhere in February 2018
>>
>>60545287
CPU cores are no more independent than GPU cores. The real GPU "cores" are the big clusters of shader units that are piped to the rasterizer and geometry units. Yea, they're really wide "cores" but you can still connect a bunch of them across a unified cache, which is basically how the Ryzen works. The only issue with multi-die is latency caused by physical distance. For HPC workloads that latency might not be a huge deal but for GPUs it'd be a problem. But it's more of a physics problem than a technical one is my point, since they've already proven they have a way to do it.
>>
>>60553895
>they can more than likely take advantage of Zen's 5 wide instruction per clock cycle.
The vast majority of code isn't specifically optimized for Intel's core design to begin with. If you just use GCC with ordinary settings (no particular -march or -mtune options) it doesn't schedule instructions to any particular µarch to begin with.

Even if you recompile your code with -march=znver1, only the innermost, tightest loops are likely to even have a chance to reach 5 IPC, and even that's unlikely. In more ordinary, random-access code, the max theoretical throughput is almost completely irrelevant, and it's all about how well the µarch can extract ILP from whatever is at hand, and there are lots of factors at play. Zen has advantages over Intel in having more cache, far stronger decoding and quite possibly better branch prediction, and perhaps a few more things, while Intel has some advantages in having a unified scheduler, generally larger OoO buffers, shorter mispredict penalty, and a couple of other things.

How these factors play out in a real program depends entirely on the program, which is the reason why many benchmarks are so completely all over the place, with both winning over the other with large margins on different programs. I've especially enjoyed watching 7zip benchmarks, where Intel wins by a fair margin in compression, while Zen wins by an equally large margin in decompression (or if it was the other way around).
>>
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>>60554087
Most retards who /game/ think IPC is something per core
They always say
>The IPC is better since games only use 1-2 cores anyway

IPC is a per clock basis
If both chips are clocked to the same clock say 4.0ghz the AMD chip is a faster chip
If AMD can crack the code on how to get their chips to a higher clock intel is over
Intel cant just keep clocking their chips higher as it loads wattage out the ass because that is how silicon works.
Maybe 7nm will be the key to AMD hitting higher ghz while running lower power.
Intel needs to improve their design at this point
>>
>>60554087
If you're going to argue IPC, at least post single-threaded tests.
>>
>>60554192
>If both chips are clocked to the same clock say 4.0ghz the AMD chip is a faster chip
That's not true, though. Single-threaded benchmarks with similarly clocked CPUs are all over the place. See >>60554190. It depends entirely on the program being ran.
>>
>>60554192
>Most retards who /game/ think IPC is something per core
Well yeah. It's called Instructions Per Core for a reason.
>>
>>60554271
It doesn't mean that at all.
>>
>>60554201
>single-threaded tests
we not in 2001 anymore, just use math to calculate it
>>
>>60554271
>It's called Instructions Per Core for a reason.
Retard alert. IPC stands for Instructional Pre-fetch Cache (multiplier).
>>
>>60554271
No, it means inter process communication.
>>
>>60554307
>use math to calculate it
Please enlighten me as to how that would be done without knowing the utilization factor. Not to mention it wouldn't even account for bus contention.
>>
meanwhile, i have virtually no reason to upgrade from my 4670k
>>
Jesus this thread tailed off in to a sunday stroll through hell with the intentional trolling triggering me.
>>
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>>60554271
>Instructions Per Core
wut
Its
Instructions Per Cycle
Or
Instructions Per Clock(Cycle)
>>60554257
Yes some chips can perform better with a higher clock because memory controllers can fluctuate ect but overall if two chips are clocked the same and one performs better its design has higher IPC
These days its more about work done per watt of power used. Servers need great performance but with little power usage.

New instruction sets change things as well since some programs use legacy version so are more adept at running old hardware or some use new once exclusively ect
Its never really as clear as it seems.

A 4 6 or 8 core Ryzen chip will age and perform better in the long term compared to intels current consumer chips.
Intel is strong right now in gaming because most game and game engines run old instruction sets or are not able to use more cores/threads as well. The newest engine games all seem to run better on AMD hardware compared to intel or NVDA
>>
>>60553939
That or the engineers are sick of their shit and won't.
Given everything intel in the past with their shady practices and forced backdoors, I wouldn't be surprised if theirs a secret tools down in the labs.
There's no fucking way they're that attached to skylake. Any engineer worth their salt always strives for better unless moral is affected.
>>
>>60554404
>Yes some chips can perform better with a higher clock because memory controllers can fluctuate ect but overall if two chips are clocked the same and one performs better its design has higher IPC
What I said, however, was that Zen doesn't perform strictly better at the same clock. In some tests it performs better, in others it performs worse, and the margins can be quite large. That's why I said it's all over the place.
>>
>>60554192
>Maybe 7nm will be the key to AMD hitting higher ghz while running lower power.
That depends on a lot of factors, mainly being the stability of the silicon and its counterparts.
You could be very well right, I'm hearing Zen can handle voltages higher than 1.4 as a daily thing.
That with some things left out of Ryzens arch that will be featured in future should help greatly with clocks.
I was disappointed with that release only in terms of max clock.
Theoretically it should have been around 4.3-4.5Ghz. Source: My Dad works at Nintendo.
But with time constraints things got left by the wayside, even samples didn't have those functioning.
Release of the APU's should provide insight to what's happening. But nothing solid. Source: Speculation by me, based on what my "Dad" has said.
>>
>>60554463
Take into account that nothing seems to utilize Zen's larger L2 caches yet, software naturally expects a shared pool of L3 cache like most Intel has, AMD's L3 is designed quite differently here, no small amount of programs is using ICC, and the others still using MSVC are so old they probably don't know Zen exists.

On Linux the situation seems much cleaner since LLVM and GCC have decent support and even older GCC versions do fine.
Kinda too much variables, that's why the gcc subtests of SPEC are highly valued since they ignore any compiler tricks.
>>
>>60554672
>Take into account that nothing seems to utilize Zen's larger L2 caches yet
How many programs are you really expecting to have algorithms tuned to any particular cache size at all?
>>
>>60554704
About all of them, thanks to a decade of 256kb of L2 of Intel domination
>>
>>60554672
>L2
Does anything really take advantage of it at all, back in Covington's day, no L2 was an advantage for games. But tanked other real computing tasks.
>>
>>60554723
What kind of algorithms are you even expecting to show any gains from being cache-aware? The vast majority of algorithms that are even written with optimizaton in mind (which is a minority to begin with) either have a fix data size or depend on stream prefetching.
>>
>>60554704

None, because control of the various levels of cpu cache isn't exposed to the kernel at all.
>>
>>60554747
Intel is changing their memory hierarchy from 256kb to 1MB L2 after god knows what in Skylake-X, so there's probably a very good reason.
>>
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>>60554779
inb4 shared L2
>>
>>60554778
>None, because control of the various levels of cpu cache isn't exposed to the kernel at all.
The cache size and organization certainly are -- see /sys/devices/system/cpu/*/cache/.

That being said, the amount of programs/algorithms that are actually tuned to take advantage of this, or even *can* do so, is going to be minuscule.
>>
>>60554779
I'll bet half a dollar that it's because they're not getting all that good scaling on L3 and it's both power hungry and hot.
>>
>>60554779
Prepare to see higher L2 latencies then.
>>
>>60554779
>so there's probably a very good reason
For Skylake-X, the reason is in all likelyhood AVX-512.
>>
>>60554835
All "IPC" microbenches are run in a vacuum and loop in the L1 anyway
>>
>>60554842
Could be, Cannonlake is still 256kb.

Thought would AVX512 really benefit from larger L2 and gimping the L3 that much? Wouldn't it be better if avx512 data was dumped into the L3 for other cores to see?

Or are we getting shared L2? That sounds retarded.
>>
>>60554891
>Thought would AVX512 really benefit from larger L2
Bandwidth -- A core can only read 32 B/cycle from the L3 cache. Not sure of the L2 cache has been beefed up for AVX512, but on ordinary CPUs, it has 64 B/cycle read bandwidth.
>>
>>60555036
In other words, AVX512 with data from the L3 cache is pointless, since it can only sustain enough bandwidth for AVX256.
>>
>>60543195
Just upgrade now and get 7nm+ in 2019, 2020 or whatever. That makes more sense unless you're already on something recent like Haswell.
>>
Apparently Lisa Su went to the gym lately. Her assigned personal trainer asked her if she was looking to lose weight or put on some muscle. To which she replied:
Just wait
>>
>>60557084
HAHAHAHAHAHAHAHAHAHAHA WAITFAGS ON SUICIDE WATCH! AMPOO BTFO! HOW WILL THEY EVER RECOVER?
>>
>>60544127
Intel never lead the way, not recently

It just so happened that AMD had major fuckups with Hector Ruinz.
Intel always copied AMD from the early 00s onward. Once AMD was no longer competitive, they had nothing to copy. Don't you get it, now? Doesn't that make it so clear?

The only reason AMD went to shit is because the failure of a decision to make Bulldozer, instead of Phenom III. Because AMD never made Phenom III, Intel had nothing new to copy so they had to keep reiterating on their Phenom II copy.

Now that there is Zen, which is basically Phenom IV if Phenom III ever existed, Intel will copy it.
>>
>>60544986
>>60544995
Well they confirmed that Vega already supports "infinity fabric", whatever that will actually mean in practice.

It may simply be how a single Naples CPU can instruct 6 Vega GPUs, and the GPUs can peer2peer, without a PCI bridge thing. I forget that details of that, but apparently it's a huge deal in that space.

>>60554201
How well the SMT performs is an IPC increase. Arguing otherwise is stupid.
If your clocks are sitting there doing nothing, not cycling, waiting, that is ZERO IPC.
>>
>>60557311
>Well they confirmed that Vega already supports "infinity fabric", whatever that will actually mean in practice.

IF means two things. Firstly it means the new transaction-layer coherency protocol that's replacing HyperTransport. Secondly it's the physical 256b crossbar design plus the GMI (interposer) and xGMI (inter-socket) links between crossbars.

Vega doing IF means hybrid MCM APUs, with Zeppelin and Vega chips being able to share memory at latencies and bandwidth nearing same-die setups.

It also potentially means that Ryzen/Threadripper/Epyc chips and Vega AICs will be able to talk to each other using xGMI controllers on the PCIe slot lanes, accomplishing the same low-latency communications (bypassing PCIe controllers/stack) albeit at comparatively low bandwidth (~16 GB/s).
>>
>>60544975
Chances are high its going to use AMD's InfinityFabric and have MGPU on a single board, working as a single unit. That's what they're doing for Epyc and if it works well on the GPU side, it'll make the most sense to do it on that too.
>>
>>60543632
Intel shills are still using this completely false arguement
>>
Until they can get their 4 and 6 cores up to at least 4.5 ghz I'm not interested
>>
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>>60553939
>4.5 ghz 7700k is the same as a 2600k

It's a bit more nuanced than that
>>
>>60544161
>They ignored their core market and tried everything to break into mobile. Didn't work

But they sure tried. I actually do have a 7" Intel Atom based tablet. It was dirt cheap thanks to Intel giving away their chips for free to get them into as many products as possible. They had a hard time getting anyone to accept their chips even with this - again - highly illegal behavior.

Why? I never use my Atom tablet. Ever. It's a slow piece of trash. Slow as in extremely slow. The battery life on it is a joke. It will overheat and shut down if you do anything demanding on it. I haven't thrown it away but I guess I should (not that it takes up space) because I never ever use it. Any cheap Mediatek or Allwinner tablet is superior.

This actually says something about how far behind x86-64 chips are in terms of heat and efficiency compared ARM chips from small little-known companies.

Quite frankly.. AMD isn't going to be Intel's biggest problem in the future. The progress Qualcomm and the rest are doing will probably result in them taking over the entire notebook / cheap laptop market.
>>
>>60559190
> OC 4.7GHz
What sorcery is this
Mine hits 70 on 1,3V@4200
>>
>>60553939

i5 - 2500k

1.16 billion transistors

i7-7700k

1.7 billion transistors

That's a huge fucking difference. Do you understand how computers work?

Also, for what its worth the 1800x has 4.8 billion, same as the 1700
>>
>>60559276
Sillocon lottery, also I'm sure he went a heck of a lot higher than 1,3v, probably closer to 1.4. Sandy Bridge can take it.
>>
>>60549011
>brings to mind the lamest possible marketing department.
AMD don't have a marketting team.
They fired them for being shit.
>>
>>60559288
>i5 - 2500k
>1.16 billion transistors
>i7-7700k
>1.7 billion transistors

most of that increase is from the IGPU
>>
>>60543377
>>60543530
>intel 10nm will be slower than 14nm
>>
>>60559395
>but still faster than AMD
>>
>>60559444
Ha ha no 7nm IBM is HP and it clocks like a monster fitting for POWER.
>>
>>60559558
U w0t pajeet?
>>
>>60559658
Ha ha it's a process designed to power the kike burning ovens called POWER10. And restroactively power another Shoah called Zen2.
>>
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>Intel's fab advantage turned into a disadvantage
>>
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>>60559444
it isnt faster right now pajeet
>>
>>60559882
>it's a process designed to power the kike burning ovens
It sure delivers enough heat to do so.
>>
>>60559444
When you and your fellow travellers realize just how large the performance gap is going to be between AMD 7nm at monster clocks (the process is IBM's and is designed for high clocks) and Intel's 10nm which is SLOWER THAN 14nm, they're going to have to hide every shoelace in Israel. Fucking kikes are going to start gasing THEMSELVES in shame.

You have no idea how fucked Intel is when 7nm Zen2 hits and Intel is stuck in their dumpster fire of an uarch until 2021.
>>
>>60544596
>2020
>still no graphene
>tsmc still playing around to milk silicon at 5nm
>>
>>60545428
>the shit wrecker hits the gym
>everyone follows
no fatass on shit wrecking team.
>>
>>60554192
>If AMD can crack the code on how to get their chips to a higher clock
it's not a code.
just move from lpp to hpp.
>>
>>60560819
>tsmc still playing around to milk silicon at 5nm
>(((5nm)))
>>
>>60560819
>>60560941
it's not like 5nm on silicon is impossible, it's just copper that's the limit
silicon photonics is probably going to be the next step
then switch to graphene in a decade
>>
>>60561029
>it's not like 5nm on silicon is impossible
Neither is that what I tried to imply; merely that TSMC's 5 nm process is likely to be anything but.
>>
>>60561046
oh yeah totally they'll just take 7nm, wait for the process to mature or add EUV and then call it 5nm
>>
>>60561029
>silicon photonics
I wonder why you think this is going to be a thing for random logic. Silicon photonics is a technique for integrating fiber-optic interfaces directly onto a die with otherwise ordinary silicon logic. It's not like there's some kind of "photonic transistor" or anything.
>>
>>60561081
I'm saying it's to replace copper wiring with photons
>>
>>60561215
What copper wiring are you referring to? The interconnect? You know that you require a PHY for every conversion between an electric signal and an optical signal?
>>
>>60561263
yes, the interconnect
there have been a few paper about implementing it in bulk CMOS and I think IBM actually had manufactured some test chips with germanium photon receivers
shitty internet connection atm, I'll link it later when I'm home
>>
>>60561438
>I'll link it later when I'm home
Please do.
>>
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>>60561438
>>60561683
Thread posts: 242
Thread images: 32


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