Ryzen ccx explanation

>there

>>59694450
It's essentially two seperate 4c/8t CPUs on one die, connected by a crossbar. The crossbar's frequency is 1:1 with your RAM frequency, so the shitty early BIOSes that could only boot 2133MHz RAM also massively slowed down that interlink. Now that it's possible to boot 3200MHz+ RAM (with the right kits), gaming performance has massively improved, something which is a direct result of the frequency of that interlink also being raised.

https://www.youtube.com/watch?v=RZS2XHcQdqA

As for why it's designed this way, scalability in the server market. Ryzen is primarily a server design at heart, because AMD want to win back that market even more than the desktop one. This also partly explains the low clocks and why it's SO efficient at low clocks. The cores use an obscenely low amount of power once you get down towards 3GHz, which is why the 1700 has just a 65W TDP. For an 8c/16t chip, that's pretty nuts. Intel's comparable chip is 140W with a 3.2GHz base clock.

>>59694450
Ryzen performance in games was hampered by shitty Nvidia drivers.

>>59694520
so two 4c8t got stuck on one die and that helps with serverstuffs? thats cool.
does that mean the processor isnt going to preform that well if the ram isnt that fast?

so there is a slight possiblity that they could have just shut off one 1 ccx module for the 4c8t processors?

also do arrangments of the ccx things change preformance any?

>>59694629
Baseline performance is what it is (you can judge for yourself), but faster RAM sees a very large uptick, yes. Even the difference from 2133MHz to 2666MHz (which most boards can do with any RAM now) is significant, especially in games.

As for the R3 chips, I don't know. The R5s will just be the R7 die with one core disabled in each CCX though, plus some cache on the lowest end model (the 1400). Though the 1500X and 1600X will have all 16MB L3 cache, meaning they'll actually have more cache per core than the R7 chips.

No idea about your last question. You'd have to ask an AMD engineer.

>>59694727
well, on the last question i was just wondering because i was looking some of the stuff up and i kept sawing stuff like ryzen r7 2+2 or 4+0

>>59694750
Well, the only configuration that's going to make a difference is one CCX being disabled entirely. A 2+2 wouldn't be any different as it'd still be using the crossbar. I haven't really looked into people disabling one CCX and how it affects performance. I'm sure you can find some benchmarks if you go looking.

>>59694973
oh ok
ty ccxbro

>>59694520
This post is 99% right, with just the clarification needed that the IF crossbar is 256b running at half the nominal DDR interface speed. AMD could have made it faster and/or wider, but most workloads wouldn't benefit and power would go up substantially.

There is IMO a strong chance Naples will have to clock the crossbars at full rate (2x higher) to keep from choking though.