lets get this shit started >3+3 >2+2 rip ryzen

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Damn AMD had a chance to release the modern day version of the Celeron 300a and they blew it all to save money. A <$200 4+0 configuration would be on par with an 7700k for gayms and good for productivity. It would have been the new 2500k. Looks like the first round of Zen only yielded one good CPU, the 1700 oh well that's a pretty damn good one but still thinking of what could have been more is pretty bad.

It makes sense in its own way. It gives the remaining cores more L3 cache which can be a nice improvement. It also spreads the cores out so they don't concentrate the heat into one area and need to throttle down.

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>>59432239
For gayming it's a strict downgrade vs 4+0 and nobody interested in producticity would get anything less than a 3+3. Basically their entire line is garbage except for 1700 which is an exceptional bargain and 1600x which may well be too. Pic related is actually better than what you'll get out of any r5 2+2

>>59432278
The only one that suffered a huge penalty is BF1 which is optimized for MORE CORES. Compression likes high memory bandwidth so 7zip going up is exactly what you'd expect.

I'm going to wait for the reviews to come out before I judge them.

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>>59432365
BF1 is more likely the kind of performance you're going to get going forward tho and keep in mind this test was done using an 8c/16t part which means it has double the l3 cache so you're going to see worse performance from 2+2 r3 and r5. I imagine 10% - 30% worse.

Again, 1700 and 1600x are amazing. 1800x fits a very small niche. Everything else is staggeringly awful.

>>59432487
what the hell are you on about? 2+2 has the same as 3+3 and 4+4, all L3 is coherent across the entire CCX. They'd need to actively disable the cores and the L3 which is real dumb when it comes down to getting better performance from the chips.

Also, the reason it was kept 2+2 and 3+3 instead of 4+0 and 4+2 was to keep things the same down the line. Every dev and their mother is going to be coding to take advantage of the Ryzen design with the CCXs being slow to talk to each other but very fast to talk inside the CCX itself. Might as well keep things simple for developers.

>>59432487
I see it as a minor hindrance at the moment but it will gradually become irrelevant. The interlink between the CCXes scales with memory speeds, it's a problem right now because nothing required high memory speeds before and memory speeds are still lagging behind but as memory speeds improves the interlink will also improve.

I don't believe they're going to use 2xCCXes for everything anyway. It doesn't make sense on Raven Ridge where half the die is going to be an iGPU. There will likely be Raven Ridge chips with the iGPU lasered off like they always do.

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>>59432559
My mistake only 1400 is half cache but you also factor in lower boost clocks so no matter how you look at it the r3 and r5 will be even worse than indicated.

And the consistency excuse is just that. 4+0 wouldn't need any special instructions. The reason is simply about being able to offer more tiers for less money. Unfortunately they only produced a single worthwhile tier so their strategy doesn't make any sense.