This is my wife, please say something nice about her.

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Also very cute.

>>59143667
whats very cute about this design is that we don't have to worry about shorts between drain and source. This is a very COOL design!

>>59143464
Your wife looks like a dick.

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>>59143667
>>59143704
Low heat! Low Size! High CUTE!

>>59143464
>Not a dynamic logic gate

>>59143464
Bender you're a nasty fuck

>>59143736
That is not a nice thing to say normally, but I assume you meant it in a nice way! Thank you for the cutepliment.
>>59143749
I don't like dynamic logic gates. I don't like sequential logic either. Static cutienatorical logic is the best!

>>59143765
>when you port your signal to the wrong input and she outputs an unexpected state
how lewd

>>59143768
>but I assume you meant it in a nice way!
I did not mean it in a nice way, your wife really does look like a dick.

Also, you're cute :3

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>>59143786
Cuteness and Computeness are the most important qualities anyone can have!

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>>59143768
Wait so these different kinds of logic serve different purposes? Could perhaps some code only run on certain kinds of logic gates or whatever?

>>59143819
Having your code run on the cute gates is the whole purpose of the decoder and machine code! Your high level programming language is translated into a lower level language which is programmed into assembly which is a set of analogies and symbols for machine code which is really just a set of op codes and addresses which are just clever sets of switches to turn on or off!

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>>59143805
I agree!

>>59143866
Ai-chan has very fake forced reactions sometimes! However its the actual implementation of cuteness isn't a concern, since cuteness is an abstraction!

Im CUTELY going to sleep now! Please keep my thread up and cute till I wake up in 2 and a half cute hours! ヽ(｡･ ω<)ゞ

I wanna try dynamic logic now.

>EEs using animeNEET speak

god damnit

>>59143464
> someone will actually turn this into hentai

>>59144407
CutEE :3

Is cuteplementing a multiplier with a barrel shifter a good idea? You could send all shifts/mults to it.

>>59143464
THICC

Nandalicious.

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>>59143464
ur wife is qt
same something nice about mine nao

>>59147658
HHHng
I can almost smell that scent.

Tree adders can go suck a fuck. I will never get an intuitive understanding of them, I will be resigned to merely know they exist

>tfw verilog isn't discussed on /g/
>fags still argue all day about IPC and overclock frequencies
So what's the best way to get a job as a processor designer?

>>59143464
What's this gate?
I see an OR gate on top, and a NAND gate on the bottom, making the hole thing AND( OR(A,B), NAND(A,B) )
Is this some EE specific meme I don't know about?

>>59148890
It's a CMOS NAND gate. The upper transistors are to reduce power consumption I believe.

>>59148717
It's hard to get into if your not schooling for it. I'm a EE hobbyist, have been for years now but had my mate not attended a program and shared syllabus and textbooks with me I would only be vaguely aware of it.

We demand ethics in hardware journalism
#GateGate

>>59149315
Yeah, my program is CS with a focus in computer architecture, which is probably the only way I'll even stand a chance of getting into the field.

>>59149365
I demand a hotel dedicated to all the retarded controversies that happened the past couple years.
#GateGate

>>59149183
No. The upper PMOS are to pull the output to VDD

As an EE you're all retarded kill yourselves

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Electronics are c-cute!? CUTE!
http://www.crunchyroll.com/anime-news/2012/04/17/video-theres-no-way-my-circuit-board-is-this-cute

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>>59143464
Your wife has nudes all over the internet and my job is to lay her out.

>>59148717
I'll discuss verilog with you, what do you want to talk about?

>>59151965
kek

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>>59151296
No

>>59152163
So we used quartus in my processor class and that piece of shit software would do some pretty dumb things to your code. For example, let's say you misspelled the name of a wire, it'd go and synthesize it anyway instead of erroring out, leaving you with a bunch of dangling wires. I found things like that to be pretty annoying.
Also, is there a good way to test out a MIF file on your computer without loading it onto your board?

>>59153465
God I hated that class. We used quartus as well. For my final project we were supposed to design our own project on an FPGA. I'm a moron so I decided to program the board to solve a differential equation with the Euler method, which is iterative. When the board is programmed it unrolls all loops in the code, and mine ran 1000 iterations. As a result it took 15 minutes every time I wanted to test it and I couldn't even get it to work by the deadline.

The projects were presented at an engineering fair where people could walk around and test them, so I just left it unplugged and put it somewhere inconvenient. I pretended everything was fine in the write-up and got full credit.

Fuck hardware languages.

>>59143464
you're wife's an [spoiler]xor[/spoiler]? Is that the joke?
>tfw never taken EE

>>59151796
what kind of FPGA does this have? Do they come pre-soldered?

>>59154023
Damn that sounds intensive. I didn't know quartus unrolled loops, but in retrospect that seems real fucking necessary, what to get it all into gate logic form.
Do you know how verilog gets translated to real hardware? It's not like Inlel and Ayymd are testing their 4.5GHz chipsets on FPGAs, right?

>>59154295
My CUTE wife is a CMOS NAND gate!
>>59154301
>>59154023
>>59153465
>>59152163
>>59148717
Fuck verilog, VHDL ONLY!

>>59154301
Sure they do. It's all the same shit copied a million times, so the early tests can just be done on an FPGA until they're certain everything works. The scaling process is probably pretty involved as well, but most hardware verification is done in SystemVerilog on FPGAs or simulators/emulators.

>>59154580
VHDL is not cute

>>59154655
VHDL is cute, its an acronym inside of another acronym!

>>59154700
GNU motherfucker

>>59154766
What does GNU stand for!

>>59143464
>wife
>my

>>59154955
GNU's Not UNIX!

>>59155013
What is UNIX?

TTL is cuter than CMOS

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>>59143464

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>>59143464
>>59143667
>>59143704
>>59143736
>>59143745
>>59143749
>>59143765
>>59143768
>>59143777
>>59143786
>>59143805
>>59143819
>>59143847
>>59143866
>>59143880
>>59143908
>>59144032
>>59144407
>>59144624
>>59145584
>>59145614
>>59146806
>>59147548
>>59147658
>>59147873
>>59148692
>>59148717
>>59148890
>>59149183
>>59149315
>>59149365
>>59150220
>>59151189
>>59151296
>>59151796
>>59151965
>>59152163
>>59153064
>>59153114
>>59153465
>>59154023
>>59154295
>>59154301
>>59154580
>>59154655
>>59154700
>>59154766
>>59154955
>>59154977
>>59155013
>>59155475
>>59157929
have some free (you)'s

How's it feel that your wife is going to be irrelevant soon?

>>59158341
how so

>>59158400
well not irrelevant but won't be able to scale past the next few years

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>>59158341
>>59158400
>>59158455
hoe to i delet syestm32 ?

>>59143464
SNAKEEEEEEEEEEEEEEEEEEEEEEEEE

TAKE YOUR ADDERALL

>>59153465
>For example, let's say you misspelled the name of a wire, it'd go and synthesize it anyway instead of erroring out, leaving you with a bunch of dangling wires. I found things like that to be pretty annoying.
Pretty logical if you ask me, it'll give you a warning though, read the logs. Also if there are dangling wires some things may have been optimized and tied to a constant voltage so be careful it's not a good sign. These are not annoying these are the differences of hardware description languages from programming.

Are you using memory as an IP? Even if you don't you can write your own testbench to load it.

>>59154023
>When the board is programmed it unrolls all loops in the code, and mine ran 1000 iterations.
What does this mean? Why are you writing for loops in HDL? It sounds like you did something wrong.

>>59154301
FPGAs usually have many look up tables which are basically D flipflops with decoders, so your logic is usually implemented as a look up table. But they also have basic gates adders and anything you'd have in an ASIC library really. When you synthesize/p&r a design on an FPGA, you'll get RTL schematic you can check that to see how things are realized. You should also get another verilog netlist file which would have all the library elements used in the design, but it's usually easier to follow the schematic.

AMD and others do prototype in FPGA but the parts that operate at 4.5GHz is usually only the ALU which are often custom designed. For everything else a 1-2k FPGA will be more than enough. For ALU design they may even be using analog simulators like spectre or hspice, but I've never designed one myself.

>>59158544
>1-2k FPGA
I meant 1-2k$ FPGA for example Virtex 5

>>59148717
>get a phd in computer architecture
or
>get at least a MS and take VLSI classes, Computer architecture, and maybe catch a job at a semiconductor company
>work way up from wherever they place

>>59143464
Your wife's a tranny?

>>59158455
Yeah fair enough, interested in seeing what new technologies emerge.

>>59158754
maybe 3dpd dies

>>59158772
what

>>59158934
xd

>>59158934
http://www.silicon.co.uk/workspace/micron-readies-stacks-of-ibm-3d-memory-chips-48294

>>59158952
Ah I heard about 3d stacks.
How is power dissipation dealt with?

>>59158970
honestly no idea. I don't think they're packed as tight though

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>>59143464
Face it, transistors are just a passing fad.

>>59158987
I think its kinda cool, what improvements does DDR4 have over DDR3 other than 3d dies?

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>>59143464
This is an intel atom. Say something nice about it.

>>59159060
That circuit aint cute.

>>59159025
a shit load more space for transistors. Hopefully SSD's will also start getting cheaper soon as well.

Not sure if they're applying it to processors yet.

>>59154023
>tfw you dont know how hardware works
use state machines not for loops you codemonkey

>>59154023
>yfw you realize hardware design is inherently concurrent and not procedural

>>59154301
>It's not like Inlel and Ayymd are testing their 4.5GHz chipsets on FPGAs, right?
Well they're sure as fuck not rolling out the millions of dollars to make a new 14 nm mask set for each revision.

>>59158594
>yfw Jim Keller just has his B.S. in EE