VHDL or Verilog?

>>55928839
no thank you

>>55928839
AHDL

vhdl because types

>>55928839
Verilog was the first programming language I encountered.

>>55930631
My condolences

Modern world , aka government, uses mostly vhdl with some systems verilog for older FPGA designs. All ASICS are mostly wrote with vhdl as well

Verilog. Easiest to learn and get basic shit done with. You can always pick up VHDL later.

VHDL

>>55930639
Yeah, it was pretty miserable since I had no coding background prior. Although, I at least knew what combination/sequential logic and state machines were.

>>55928839
HardCaml/Clash

but really System Verilog is fine, with VHDL if you are doing a design that is sufficiently large.

>>55928839
sure.

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602KB, 963x720px

>>55928842
>>55928844
>>55928988
>>55930631
>>55930639
>>55930654
>>55930671
>>55930692
>>55930697
>>55930718
>>55930971

Can someone explain the difference between the two. I've used both (limited experience) and I would like to get into FPGA stuff more. But I'm not sure which is more advantageous to use