if no part of the transistor actually measures 14nm, why the

>>55875125
Isn't the 14nm the gap between the sides of the transistor?

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>>55875160

no

>>55875125
CPP and MMP are not the only metrics of a transistor. Both of these are back end. Fin pitch and gate pitch describe the height of the Fin in a FinFET structure, and gate pitch is the distance from the edge of one structure to another.
The metric you're looking for is gate length, and most are roughly near the marketing name of their given node. RMG lithography always creates a slightly larger structure due to how its etched, gate first methods produce a gate structure that is typically smaller. There are exceptions to everything however.

Physical gate length on intel's 14nm process is about 20nm.
Samsung's 14nm produces gates that are nominally very close to 14nm.
GloFo's 28nm produces a 25nm gate.
TSMC's 28nm produces a 33nm gate.

Prior to recent generations things were far more complex. Basically everyone is going off of ASMl/ITRS guidelines.

>>55875160
No.

>>55875228
>GloFo's 28nm produces a 25nm gate.
Over achieving.

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>>55875269
Just a result of being gate first instead of RMG.

>>55875228

thanks for the explanation

>Physical gate length on intel's 14nm process is about 20nm

any idea of what the gate length will be on their 10nm process?

>>55876381
20nm probably.