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GTX 1080 Ti/GP102: HBM or 384b GDDR5X?

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Given that Nvidia is already planning on binning GP100 Tesla cards for defective interposer assembly (cards shipping *this Winter*), what are the chances that the consumer GP102 will really use HBM?

> http://www.anandtech.com/show/10433/nvidia-announces-pci-express-tesla-p100
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>>55191829
It's gonna be 384b GDDR5X at 10-12 GT/s for 480-576 GB/s.

Enough to compete with a 2x-3x HBM2 card, but a lot toastier.
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>>55192132
Sweet spot for 1st gen 14/16 nm enthusiast cards would be 400-450 mm^2 with ~500 GB/s bandwidth, which is basically 2x a RX 480 or 50% beefier than a 1080.

This could be done with either HBM 2 (more cost for lower power) or GDDR5X (more heat for less cost).

The 2nd gen. 14/16 nm cards (600 mm^2 spiritual successors to 980Ti/Titan X and Fury) that come out next will almost have to use HBM2 to get enough bandwidth though.
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>>55192456
>>55192132
They will have shit latencies, who gives a fuck about bandwidth if it's all super slow. My retarded friend bought a skylake system with useless 3200mhz ddr4. I told him to find a used sandy bridge, with its superior ddr3, but no. Muh reliability muh ipc muh warranty was all he could say. Anything over ddr3 is a meme.
>>
>>55192984
GTA 5 has huge gains from both DDR4 and Skylake. Shame that Skylake-E doesn't exist yet since it also benefits from more cores.
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>>55192984
Latency almost don't matter on Skylake due to the strong memory controller present. High frequency, DDR4 paired with Skylake is the best possible combination right now.

I'm afraid you're the retard.

>>55193045

Not only GTA V, Fallout 4 and other games too.
There are several reviews of the benefits of high-speed RAM.
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>>55192984
the vast majority of DRAM latency is from opening/closing rows in the capacitor arrays and from selecting the columns in a row to read.

the external interface (DDR/GDDR/HBM/etc) matters very little, and it would be nice to see where you're getting your information that stacked memory will be slower.

that said, GPUs are designed to be very latency tolerant, and you can have many thousands of theads being juggled over the whole chip with dozen of clock cycles between operations on any given thread.
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>>55192984
I don't think you understand how memory latency works. I assume you're just looking at CAS latencies and making a judgement based on that, when latency is actually determined by clock speed as well. A 3200MHz kit at CL16 will have lower latency than a 2133MHz kit at CL11, because one number means nothing without the other.

The 3333MHz CL16 DDR4 kit that I own registers latency of 44.8ns in AIDA64's benchmark for example, which is better than the 1600MHz CL8 DDR3 that I had in my previous system.
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>>55192984
>superior ddr3
Merely pretending to be retarded?
>>
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>>55192984
>imblying
Thread posts: 10
Thread images: 3


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