Verilog Help

module exp3veri(x, y, a, b, f);
  input x, y, a, b;
  output f;

  wire nXAB;
  wire YAnB;
  wire YnAB;
  wire XnAnB;

  assign nXAB = (~x & a & b);
  assign YAnB = (y & a & ~b);
  assign YnAB = (y & ~a & b);
  assign XnAnB = (x & ~a & ~b);

  assign f = (nXAB | YAnB | YnAB | XnAnB);
endmodule

If this doesn't work, your logic is incorrect.

>>54866780
wow you are right. i guess my logic is wrong. fuck i just been wasting like 5 hours cuase of this. fuck me in the ass.

>>54866942
Should've used VHDL

>>54866780
>>54866942

nope. i am just an idiot who doesn't understand how Xilinx works. I was not actually running the simulation. just going off the test bench where the value of f doesn't change.

holy fuck fuck me.

>>54866967
It takes awhile to get used to the weird tools in the FPGA world. No worries. At least you figured it out.

>>54866989
thanks for the support


thanks for the help if there is more than one person here. i appreciate it.

>tfw 3 weeks working on a real-time image thresholder
>finally finished

Feels good desu

>>54866212
You know you are suppose to describe the logic on a higher level than basic bitwise arithmetic with things like verilog/vhdl right?

>>54866212
>I have been bashing my head against the wall for like 5 hours trying to get this simple Verilog circuit to work.
http://danluu.com/why-hardware-development-is-hard/