Altera Cyclone

>>1076308
Yes

Huh, rare to see fpga shit on /diy/ or 4chan in general.
Uhhh. Hmm. Yeah my first step would be to check if the cyclone has enough GPIO. I haven't worked with the 2 but I know the 4 can have like at least a hundred GPIO pins.

Eagle is pretty popular.

Might want to try an evaluation board before you build a whole PCB, I think a Cyclone IV/V runs about 90 to 100 dollars at the moment.

>>1076308
>opencores.org for hard IP

Uhh breh that shit ain't hard

>>1076349
oh yeah, i'll just skip the dev board. they're pretty much only for blinking LEDs.

Quartus is free. and then I already have Simulink and MATLAB. so i'm just going to synthesise the circuit before I pay any money. I know the chip im studying is just an old 8bit 3mhz hitachi MPU with three 8 bit data busses. so even running a cyclone at 25mhz it should be fine sampling it.

I just wish people had pointed me towards EDAs earlier. they didnt even teach this at university. it's considered PhD tier stuff when the program just basically writes itself if you generate the IBIS and definition files which are easy enough. people pretend to be hacker wizards like they're doing it all in a hex editor.

>>1076398
Wut. Dev boards typically have GPIO access. Why would you hurry to fuck something up by skipping the development process? Why does this need to be a custom PCB just for testing 1 chip?

>>1076398
>if you generate the IBIS and definition files
what are those?

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1MB, 913x488px

>>1076423
that's fine for RS232 or some other low speed protocol in the couple of khz range. but for higher speeds you end up with line crosstalk, capacitance and path distance matching problems. the simulation software will generate a board for me with matched i/o lines so that bits dont flip and they arrive at the same time on the parallel interface in layer 1.

>>1076453
IBIS is a standard signalling definition file format. when you're simulating a circuit you can get their simulation files or in this case, its a chip from the 80s before anyone did that, I have to make my own. the advantage here is that I just read the datasheet for the chip im analysing and program how it gets signals into a file. the simulator then knows how it can be connected to another chip. in this way, on another chip i want to connect to it, for which i already have the simulation files for, i dont even need to think about how to lay out the lines, of which there can be hundreds, you just draw symbolic links between the chips like drawing a straight line in MSpaint. then when you compile the simulation it just works out how to place the parts and draw the traces, how big, how long, how they can be drawn to all be the same length and meet separation requirements etc.

this is how engineers actually work because they need to make a whole thing in less than a month then pass it on to software developers, market testing etc. to get the whole product to market in less than 3 months.

>>1076473
Oh okay I gotcha. I know a little bit about higher frequency and RF design I just didn't apply it to this situation.

Do you have a service to pick and place and print the board for you?

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6KB, 237x295px

>>1076473
>when you compile the simulation it just works out how to place the parts and draw the traces, how big, how long, how they can be drawn to all be the same length and meet separation requirements etc

>MFW every autorouter I've used produces unusable garbage

>>1076473
Nigga you just need a logic analyzer. Since you are so into the fpgas, try this https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/

http://ebay.com/itm/20pcs-single-row-needle-male-pin-header-1x50p-50pin-1-27mm-pitch-straight-NEW-/271877696991

I recently ordered these, they're a lot cheaper than digikey

>>1076498
have you by chance used any EDAs that typically cost more than $5k/ station license? companies typically dont shell out that much money for something that doesnt work on a continuing basis. Quartus is only free in the lite edition because all the multi-user, high end chips and distributed compute functions are disabled so its pretty much a guy in his garage level of utility.

>>1076526
thanks!

>>1076516
that looks good. I need more i/o pins though and well, i/o. I am scaffolding my way into FPGA development. first stage is to build a logic dump for this chip, then I want to build a test bench for the stock ECU, being able to send signals to it to make it think its in a running car, then I want to start manipulating the I/O. but the best way to do that is to start by mapping it. because it's so old, when they were first making EFI units they just took audio processors and used those. but its not just one MPU, there are four chips, three of them seem to be programmable "pulse processor units" so i really need to find out how they respond to changes in sensor signals which means synchronising the data from about 100 test points. but that's far in the future. first i just want to do something much simpler.