http://www.androidauthority.com/who -will-be-the-first-manuf

File: nm process details.png (31KB, 707x797px) Image search: [Google]

31KB, 707x797px

>>61525126
Brian JUSTnich is a terrible CEO. Him and his beancounters that are running the show are slowly driving the company into the ground.

>>61525126
>AMDtards shilling for rypoo again

>>61525126
They're fighting Apple, AMD, Qualcomm, Samsung, Global Foundries, and IBM, and they've enjoyed virtually no competition for the last decade so they haven't put in the R&D to stay ahead.

>>61525234
This is what retarded fanboy shitposters like >>61525201 don't fucking get. It's not even about AMD anymore. Intel is about to get fucked from all sides for their complacency and over-reliance on their fabs.

>>61525183
This.
Does anyone have a translation of that CPC Hardware article?

>>61525309
>They have internal sources at Intel and the climate there is currently awful apparently, employees are very discouraged and some feel like "they have nothing left to lose". They are making big profits now by totally screwing up the future. According to the magazine, Intel is "probably in the most delicate situation it has had to face to this day". The CEO is reducing cost so much that he's managing engineers like "supermarket cashiers", he doesn't care about taking the time to train them.

>Krzanich is very impatient and eager and keeps changing his mind about projects. If a new architecture isn't created in like a couple weeks, he gives up and cancels the project... he keeps sending contradictory instructions to the teams.

>"Fab Hell": Intel is likely going to have a 6 month delay on 10nm. Worse, even Cannon Lake is not expected to feature any significant architectural improvement. Basically Intel was just hoping AMD would keep not competing with them.

>In the picture before the last picture I posted, it is said that Kaby Lake has exactly the same IPC as Skylake. No improvement as to perf/watt but there seems to be more room for overclocking.

http://imgur.com/a/qo9pH

>>61525126

Only if you believe the marketing slides that say its "7nm". Besides, after FinFET, measuring things like gate length is pointless. The nanometer moniker to measure feature sizes has been irrelevant for some time and needs to be replaced but the marketing has been so effective I doubt it ever will. These foundries will just keep making up numbers like GloFlo's infamous 20nm rebranded to 16/14nm.

In reality GF's 7nm should match intel's 10nm density.

>>61525339
120% spot on.

>>61525355
BEOL is one thing. But FEOL is also important and Intel's 10nm is far behind FEOL-wise.
>>61525339
At least Sunnyvale is not that far off from Santa-Clara.

Intel is hopefully finished and bankrupt

>>61525378
>At least Sunnyvale is not that far off from Santa-Clara.
Sickburn

>>61525339
The hits just keep coming. A departure of this scale right before they develop a new architecture tells me there's something seriously screwy going on behind the scenes.

https://www.techpowerup.com/235385/francois-piednoel-quits-intel

>>61525339
Fucking wizards predicting what would happen 8 months later

>>61525417
>the dude that participaed in R&D cycle of every non-BIBELINES Intel uarch since Katmai
Boy.
BIBELINES INCOMING.

>>61525433
Step 1. Remove "unnessecary" parts of x86
Step 2. Replace with BIPELINES
Step 3. ???
Step 4. Housefires! And profit, hopefully.

>>61525431
These wizards were the first to get BOTH K8 and Zen ES.

>>61525417
Karma Exists and you get what you deserve eventually, that's all that's happening here.

File: CdZruDB.jpg (801KB, 2552x3510px) Image search: [Google]

801KB, 2552x3510px

>>61525454
Must have some nice connections in AMD.

And this is the first time I've seen such a detailed kabylake frontend, these guys actually give a shit about technology.

>>61525478
>512kb L2
>victim L3
>Kaby Lake
?

>>61525201
I'm using i5 3570k

>>61525478
That's Zen, look at the 2 AGUs and 512kb L2

>>61525126
helps when you piss off ibm and they decide to push their money into new nodes...

By the way, looks like IBM is going to adopt HBM too.
>>61525339
>Basically Intel was just hoping AMD would keep not competing with them.
Then there's no hope left.

>>61525478
5 decode/cycle
1 more AGU
another FPU port
Increase FP register sizes to skylake levels (184 IIRC)
Increase cachelines from 32bit to 64bit
Lower l2/l3 cycles by 5-10%

Here I see a rather simple way to get another 10-15% IPC without even touching the uOP cache

It's really amazing how AMD managed to so much with so little

>>61525567
This, and let's not forget the insane efficiency of Zen.
I wonder if they can significantly lower the uncore power draw.

>>61525567
>bit
byte*

>>61525567
I hope AMD goes nuclear with Zen2, technically they could build the zeppelin die somewhere around 115-125mm^2 on 7nm.

But what if Zen2 is the same size as zeppelin?
What if it's actually bigger?
If it's bigger, I think Intel will start considering something more drastic than suicide

>>61525676
>considering something more drastic than suicide
Suicide with bibelines?

>>61525691
Dark alley Skylake-X meetups where they call upon Satan to liberate their souls from this suffering

Featuring the new and improved Skylake-Xv2 22 core

>>61525339
The l2 was probably a desperate measure to improve performance.
In theory doubling l2 could improve performance but as a trade off they killed inclusive l3, and the mesh... Well in theory it could make things better at big core count but the results aren't quite better.
Perf improvement over Broadwell is almost zero, and cutting prices will accelerate downfall.
Unfortunately Intel isn't bringing anything new, and everything new is a flop, optane, knight landing, and so.

The so fabled 10nm will not improve performance is probably the worse part.

Are laptops going to have Snapdragons soon as their processors?

>>61525733
hopefully.

tired of intel's jewry.

>>61525676
they gonna hold the retailers hostage threating to fire up 7900x while doing automatic OC with a passive cooling solution

>>61525733
No, as long as Zen exists.
Unless you're talking Chromebooks n shiet.

>>61525733
That's already happening. http://www.pcworld.com/article/3191401/computers/qualcomm-first-windows-10-arm-pc-coming-in-the-fourth-quarter.html

>>61525749
Zens coming to laptops? Intel have been too long the only option for laptops.

>>61525767
>Atom-tier performance
But why.
Even 2/4 Zens would be better.

>>61525776
>Zens coming to laptops?
Yes.
That's not suprising considering how good Zen is at lower clocks/lower voltages.
And let's not forget about iGPU that actually has working 3D drivers and is better all-around.

>>61525778
Energy efficiency I think.

File: AMD-EHP-APU-32-Zen-Cores-Greenland-HPC.png (262KB, 550x502px) Image search: [Google]

262KB, 550x502px

I wonder if AMD will ever release pic related on market or is just making these for CERN [citation needed]

>>61525809
It's their super speshul sikrit sauce to bully the jew outta HPC market.
And it's not coming any time soon.
>>61525808
Then why wouldn't you use fucking Atoms?

>>61525201
>”Please Intel, drive AMD into the ground so you can fuck me in the ass even harder”

>>61525821
I don't know ARM doing some things better?

>>61525866
Being a botnet?

>>61525567
They've done more upgrades to Bulldozer than that over the years with barely any R&D used on the construction cores, I think they can do even better for Zen

>>61525884
No idea

>>61525417
Any news on why he left?

File: 1475198891551.gif (162KB, 300x367px) Image search: [Google]

162KB, 300x367px

>>61525809
>32 core Zen based APU
Please stop, the future is coming too quickly. It's getting hard to handle at this point.

>>61526070
No, only speculation.

>>61526085
I'm not sure they would ever sell that to consumers.

>>61525731
>The l2 was probably a desperate measure to improve performance.
>In theory doubling l2 could improve performance but as a trade off they killed inclusive l3, and the mesh... Well in theory it could make things better at big core count but the results aren't quite better.

The basic chain of logic with the former and current designs is:

> crossbars don't scale to large core counts -> use ring buses
> ring buses have longer latencies -> use inclusive L3 to keep ring traversals lower
> shared inclusive L3 causes L1/L2 evictions from foreign cores' L3 activities -> add a bunch of Cache Allocation Technology etc. bandaids
> even bidirectional single rings don't scale well beyond ~10 cores -> add overlapping rings
> overlapping rings use too much die space -> keeps rings separate and use buffered bridge between them
> inter-ring buffers bottleneck everything, and have too much latency between some cores -> use meshes! lower latencies = non-inclusive L3 possible = L2 can now be made bigger = SMT can suck a little less and AVX might do a little better on slightly larger working sets
> (you are now here)

The big ass mesh of distributed L3 is Intel's attempt to keep Xeon as the Jack of All Trades, since some things actually do benefit from having ~10-30 MB working set sizes that can stay resident in cache. However, chip-wide shared L3 just doesn't scale anymore, and Intel will be pressured to go with a clustered L3 design similar to Zen.

>>61525788
Do we have word on what AMD is using as GPUs for laptop Zen yet?

File: IMG_20170608_164519.jpg (2MB, 1872x3328px) Image search: [Google]

2MB, 1872x3328px

>>61525126
Shalom

>>61527786
It's 11CU Vega iGPU.

>>61527821
RIP shittel "HD" graphics

>>61527879
No shit.
It's 768 Vega shaders which is fucking FORMIDDABLE because Vega introduced neato things like TBR.

Just a general question, but couldn't Google deepmind ai create a much better cpu if we pumped all our current knowledge of CPUs and their functions into it and let is run endless trial and error designs?

>>61527968
No.

File: jimkeller.png (105KB, 255x345px) Image search: [Google]

105KB, 255x345px

>>61527968
>implying that Meme Learning can beat Jim "Contract Killer" Keller in CPU design

>>61527984
Why not?

>>61527968
Zen's improved branch prediction can learn and improve performance over time.

>>61528126
that is just marketing bullshit.
Branch prediction is just that branch prediction, isnt like there is an machine learning doing AI and keeping up tables for loads.

>>61528379
They used ML to train the branch prediction before they put it into the CPUs, it isn't learning while you're using it. Just the learning by itself means that if they rerelease the same chips they can get a performance improvment.

I started hating Intel when they cut their QA budget and this happened:

> In August 2014, Intel announced a bug in the TSX implementation on current steppings of Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX feature on affected CPUs via a microcode update.

At least with AMD all cpu support all instruction set extensions with Intel you have to pay a premium for them and if bugged they just disable it no money back.

Same with the recent Kaby Lake and Skylake hyperthreading bug: you get a microcode update that lowers performance just because the kikes had to save moeny and didn't test it properly.

>>61529115
Ryzen has L1 bug that causes segfaults.

>>61529115
Source on the lowered performance?

>>61525234
>so they haven't put in the R&D to stay ahead.
I'm pretty sure Intel is still the company that spends the most money in R&D. Some years ago it was the case at least, it was first in term of R&D budget and it was first by far.

File: 1490973354967.jpg (599KB, 1312x1740px) Image search: [Google]

599KB, 1312x1740px

>>61529115
>>61529181
>>61529303

>>61525831
this

>>61529739
So absolutely nothing, then?

>>61525478
>give a shit
Swearing distracted from your commentary.