https://newsroom.intel.com/newsroom /wp-content/uploads/site

>>59627229
>10++

Uh oh

>>59627229
The naming kikery of semi fabs will never not annoy me.

I wish they just called shit by the geometric mean dimensions of a NAND cell or something just so quasi-normies like me could reasonably comprehend transistor densities on the chips at a glance.

>>59627229
>10nm
>34nm appart?

Wait so what is 10 about it?

>>59627899
Merketing bullshit.

>>59627853
>>59627899
>>59628341
>I don't understand things and it makes me angry!

Process nodes are named for the minimum feature size that they can etch. Their 10nm node has the ability to draw and etch a 10nm line. They are not named for specific metrics of architectural structures, though by coincidence some structures may reflect the name in one way or another.
If you don't understand this then don't bother shitposting about it.

>>59627229
First off they will be reusing 14nm on their 8th gen cannon lake chips so this does not apply to the next intel release which is going to be a giant nothing burger like kaby lake.

However if these kikes can get yields up by gen9 then there exists interesting opportunities here. The frequency probably wont jump by very much and might even go down do to the closeness of the transistors HOWEVER since this allows them to pack triple the density into the silicon they have the opportunity to finally toss their core architecture and redesign it.

Essentially they have more room to pack more transistors into therefore instead of pushing clockspeeds to boost performance they can focus on IPC instead. Drastically increase the L1/L2 cache and the core size to push single thread performance at the same or lower clockspeeds. With the better gates they can reduce power leakage which further boosts efficiency allowing stable clocks at lower voltages.

The MOAR GIGAHERTZ meme and the MAOR COARS memes can all die and they can instead pack that silicon with cache and a larger pipeline to boost single thread IPC

They need to do that soon because Zen is a gamechange. The Zen cores are smaller and more efficient and the only limitation is the infinity fabric conecting the four core CCX's which is be fixed by gen 2. Gen 2 zen will be on a better node and push higher clockspeeds and have faster DDR4 memory support probably up to 4000mhz and its gonna have the fabric bandwidth and latency improved as well. Even if thats all that happens zen+ will smash the fuck out of cannon lake if cannon is another kaby refresh on 14nm.

neat

REEE STILL USING SHITICONE

>>59630160
>Drastically increase the L1/L2 cache

Protip: x86 is stuck with 32 kB L1D since virtually indexed physically tagged caches are limited to page size * n-ways capacity, x86 pages are 4 kB, and 8-way is the reasonable limit for VIPT caches. I-cache doesn't need to worry about virtual aliasing because it's non-coherent and effectively read-only, so that's why you see shit like 64 kB L1I in Ryzen.

>>59628503
say it however you want, the naming scheme is still fucking retarded.

>>59630692
how much longer will intel and AMD keep adding x86 to their chips? they will dump it eventually right? ARM seems to be the future at least for low power mobile apps.

>>59631426
AMD considered doing a high-perf ARM core the same time as Ryzen then canned it.

Who knows exactly why, but it's probably better for them to be 2nd string in a duopoly than to help kill off x86 even faster and have to compete in a much broader field.

>>59630160
> 14nm
> Cannonlake
GNO
I'm sorry anon I don't want to start a flamewar over nothing but this was rather misinformed.
Things don't get better
> pack more transistors
> frequency
packing in more transistors increases heat dissipation per area unit, which would force you to decrease frequency.
> toss their core architecture and redesign it.
wew
You don't just "toss" your architecture. This isn't your everyday shitty MIPS you can design in a day.
> focus on IPC instead
Implying this isn't where most work and gains are today?

>>59630160
So you're saying Prescott is back baby

>>59632622
they have two choice. increase the space of the tranistors to push higher clocks or accept lower clocks and pack transistors in like sardines to boost cache and pipeline size to up IPC

the second option is much better for low power (mobile) and Server space so thats what they will do when they next redesign their arch. Of course knowing intel they will just refresh their current arch on the new node first to up gains that way for a generation or two if ryzen wasnt lighting a fire under their asses.

>>59627229
>still 1.7% yields
wew

It really feels like they're shrinking die nodes just out of habit now.
Since really, the nodes AREN'T getting smaller, they're just changing shape.
They're getting taller and thinner, meaning their overall volume remains the same.

It's why we're not seeing massive dieshrink leaps anymore- the benefit from was reduced transistor volume, not area.

>>59628503
14nm is the gate length of the finfet.

>>59627899
They were overoptimistically with naming the last one so now they have to go along with it

>>59630160
>The frequency probably wont jump by very much and might even go down do to the closeness of the transistors
>frequency probably wont jump by very much and might even go down
You're in for a rude shock
>Drastically increase the L1/L2 cache
That ain't going to be on 'consumer' chips. Not for less than $1000 anyways.
>can instead pack that silicon with cache and a larger pipeline
Literal housefire.
Bentium disguised as i9

>They need to do that soon because Zen is a gamechange. The Zen cores are smaller and more efficient and the only limitation is the infinity fabric conecting the four core CCX's which is be fixed by gen 2. Gen 2 zen will be on a better node and push higher clockspeeds and have faster DDR4 memory support probably up to 4000mhz and its gonna have the fabric bandwidth and latency improved as well. Even if thats all that happens zen+ will smash the fuck out of cannon lake if cannon is another kaby refresh on 14nm.

The fuck, Not a lie here. I thought you were a Intel shill.

File: 1488919359748.jpg (143KB, 960x686px) Image search: [Google]

143KB, 960x686px

>>59630160
Intel is shit guys
AMD is more advanced
AMD will fix the ccx issue
AMD will fix the DDR4 support
JUST WAIT

Jesus every damn thread is the same shit

>>59633097
That shill oc again
Tearing don't just happen on low Fps.

>>59627229
Gg no re by the time AMD can pop out "7nm" designs Intel will be rocking them year after year.

>>59631426
because some of us require higher performance than using kikeberg and 4cuck

>>59628503
>Their 10nm node has the ability to draw and etch a 10nm line
That's really retarded.

I mean back when I used to design with 350nm, it really meant you were using a 350nm gate length...

File: lithot1.jpg (21KB, 300x389px) Image search: [Google]

21KB, 300x389px

>>59633699
Don't pretend to know more than you actually do, little kid.
At intel's 250nm node they only had a 200nm gate, and it only got further removed from there on.
Intel, Samsung, TSMC, and Global Foundries are using minimum feature size for the marketing names of their nodes. It is the smallest resolution they can mask, expose, and etch.

You're a bad liar, little kid.

http://semiengineering.com/a-node-by-any-other-name/

>>59633822
>Don't pretend to know more than you actually do, little kid.
I'm an ASIC designer you fucking pile of shit. at 350nm we drew 350nm gates and got 350nm gates.

>>59633822
Doesnt that picture basically prove his point?

File: tmp_8450-1490223659178387323617.jpg (75KB, 448x448px) Image search: [Google]

75KB, 448x448px

>>59634322
Ooohhhhhhhhh

>>59635033
yes

>>59632836
not precisely. the current flow is increased with the increase in fin size

>>59627899
the fin diameter?

>>59635087
Ayyyy

>>59633822
>using minimum feature size for the marketing names
Then why do they name the node 32 when they get 29 as minimum size?

>>59638642
Marketing.

File: [HorribleSubs] Oshiete! Galko-chan - 04 [720p].mkv_snapshot_06.50_[2017.03.11_12.14.40].png (771KB, 719x720px) Image search: [Google]

771KB, 719x720px

>>59630160
>LONGER BIPELINGE WILL SAVE US

No, it won't. This is even assuming they can make 10nm viable for mass productions.

>>59633097
kys shilly shill shillington

>>59627899
Looks like the space between fins?

>>59631426
It's not (hopefully). Risc V probably is. Why? It's open. ARM has an advantage, it exists now and is a standard. Notice that Qualcomm is a RISC V platinum sponsor.

Want to compete with AMD or Intel? You can't, no x86 license for yoy. You can build an ARM soc but you have to pay AMD and sign NDA's. Want to build a RISC V CPU? Go ahead, you don't need anyone's permission.

GCC already supports it. That means Linux, Android etc. No Windows, but who wants that?

>>59627229
AYYYMD POOJEETS ON SUICIDE WATCH

>>59633822
You're both playing the same card

>>59635033
No, it doesn't. The liar used one reference point, because thats the only thing he knew, and the article I attached explicitly addressed the trend in naming conventions. What this retarded lying kid asserted hasn't held true since 1997, and even then it was merely coincidental since physical gate length and the effective electrical length are not the same thing. Such a simplistic measure as physical gate length has no real meaning at all when it comes to a FinFET.

>>59640161
hmm, you don't seem as credible as the other guy.

>>59640161
yes, the trend changed /after/ his knowledge ended
all he said was;
>I mean back when I used to design with 350nm, it really meant you were using a 350nm gate length...
this statement is true, and your picture shows it was true before that point as well

his knowledge was outdated, that's all

>>59640335
Whatever you say.
Some probable NEET autist pretending to be a 50 year old ASIC designer offering his ill informed opinions on the nuances of process definitions is totally credible.
Might as well have claimed his dad worked at Nintendo since that was the entire content of his post.

>>59640439
am i supposed to take your word on that? Mr. Anonymous the Credible?

>>59634322
Look - just because you got a masters at a tier 2 doesn't make you Bob Pease...

>>59640161
Yes, it does. He said
>That's really retarded.
>I mean back when I used to design with 350nm, it really meant you were using a 350nm gate length...
And that picture shows exactly that. That 350 nm meant 350 nm Gate length. (Same deal with 500 nm.)

>>59630160

Even if AMD comes up with an amazing cpu, would they be able to command enough mfg. capacity to make enough chips to make a dent in Intel's market share?

Assuming Ryzen's kind of memory bandwidth starved design really is superior to Intel in the server market, why would they waste dies selling them into the consumer market, when they could sell them into MCM for the server market?

>>59630160
>The Zen cores are smaller and more efficient

That's only because of the design features they left out wrt intel chips, like the wider AVX units, and wider/faster cache connections.

Those may have been the proper trade-offs to make for a cpu design that seems intended to sell into the datacenter market (Not the HPC market though). But there are trade-offs in the Zen design in order to make it simpler and smaller.

>>59631426
>how much longer will intel and AMD keep adding x86 to their chips?

They won't dump it for the foreseeable future. The complex x86 decoding adds only a ~10% overhead to these massive/complex chips, and both of them are figuring out ways of minimizing its impact (ex. the trace cache)

I agree with the other anon,and think ARM has more of a questionable future now that RISC-V is out there.

ARM will probably slowly drop its licensing costs in response, and remain in use for decades.