https://www.aida64.com/news/aida64- v590-amd-ryzen-benchmark

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>>59625289
BDW-E comparison

>>59625925
That L1 bandwidth is insane.
Intel really is the undisputed king of performance SRAM cells

>>59626072
If anyone's a EE mind telling me if the current perf cells are still using 6T or have we moved to something else?

>>59625925
This doesn't seem right.

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>>59626118go
Why does it seem wrong?

>>59625289
I've seen DRAM latency drops to 55-60ns with faster memory on Ryzen, finally we have some general use out of fast memory, hopefully this market gets more cuthroat now, but I doubt it

>>59626188
If AMD can make their IMC faster next gen then the need for high speed memory will go away.

>>59626341
With AMD's data fabric design (if it's still linked to DRAM) memory speed will always be useful for low threaded applications under Windows 10.

Throwing a thread from core0 to core2 is fine, that's some 20ns and that's similar to Intel's speed, but lending a core0 thread to core6 is where it gets hairy, the latency increases by three times as it has to traverse the CCX
Faster memory significantly reduces that latency.

>>59626172
That looks like an overclocked result, not stock, NB freq displaying wrong.
SiSoft ranker is full of results like it. It'll read the CPU base frequency off the ID string, and still display overclocked results when looking for only stock chips. These figures are typical of a 4ghz~ NB overclock.

>>59625289
Has anyone tested the latency of a core reading the L3 from a different CCX? Should be interesting.

>>59626390
>some 20ns and that's similar to Intel's speed,
80ns for moving something from one core to another on Broadwell-E

>>59626425
How does that make sense? That's more than reading from DRAM.

>>59626450
>I don't understand basic memory operations
You're reading from one cache, sending it through a ring buffer, and writing it into the cache of another core.
It is a far more complex operation than arbitrarily reading directly from system memory.