Zen can't overclock on the top end SKUs, but it sure can

Passive cooled at 2.5Ghz?

>>59237227
You can probably fit 8 cores at 2.2GHz under 30W with this.

>>59237244
>laptop workstation that's not a housefire or 13 pounds

Damn you AMD

>>59237244
TheStilt said cTDP of 35w was 1.9ghz.

>>59237892
I guess I wasn't far then.

4 core mobile APUs are gonna be something impressive.

>>59237892
The current highest broadwell Xeon is 24 cores at 2.4Ghz at 160TDP

To put it into perspective, the Naples chips are gonna be the most outstanding bins so there's extra efficiency there.

>>59237972
If you do napkin math based on the data TheStilt provided it looks like 2.6ghz static frequency at 45w. 4 of those would meet the 180w TDP for the top Naples SKU. Though its likely that server dies will have better scaling than any consumer part. It could be possible for a 2.7ghz base clock chip with 32c/64t.

Intel's Skylake Xeon with 32 cores only had a 2.1ghz base clock when it was first leaked. It looks like AMD might have a significant advantage there.

>>59237972
Yes but all the uncore is already included in that, including the GMI links, and the southbridge which the xeons don't have integrated, that's extra board power for the xeons.
Adding more cores doesn't linearly increase the TDP in that case.

>>59238044
Do you know the TDP of the Intel 32 core? I was hearing something around 190-200W TDP

Question, I saw some heavy threaded workloads where the 8 core Zen got really, really close to the 10 core Broadwell and in some cases beating it, again multithreaded this is also displayed in some benches against the 6900k as well where it does a lot better, which doesn't simply compute to my head considering their similar IPC and all core clocks.

Why is that? It's 20% more cores, and I don't think the Zen FPUs or Integer units are significantly more powerful, could it be some workloads fits nicer into the Zen caches? I thought Intel paid big money for wide cores just for these edge cases.

>>59238089
The original roadmap published in 2015 stated Skylake Xeons would scale up to 28 cores/ 56 threads with a max TDP of 165w.
Though this leaked chip allegedly has 32 cores and 64 threads.
https://forums.anandtech.com/threads/intel-skylake-kaby-lake-thread.2428363/page-328#post-38586607

Its possible that TDP is higher than was originally planned given the apparent increase in core count, but I haven't seen any confirmation on that yet.

>>59238133
Every design has its nuances, some workloads will run significantly faster, even if its slower on average compared to the competition.
The Zen core can outperform Broadwell in some metrics at equal clocks. Performance is never completely straight forward.

>>59238133
Possibly some fixed function units to accelerate certain workloads.

That's why I find the term IPC weird, IPC in one workload can be 10% higher and in another 20% slower, some work can fit into caches more than others , and this skews average results if it's too focused on.

CPUs aren't that simple that you can judge their performance on a chart or two.
And this is a problem with every new CPU launch.

>>59238274
Speaking of caches, those larger L2 ones on Zen should do really nicely for Naples, software is pretty often recompiled to suit the architecture on large racks.

It's a headache when upgrading to something totally different though, hence why you rarely see someone move from x86 to POWER/SPARC or vice-versa unless there's massive TCO benefits

>>59238133
Zen's SMT is significantly better than Intel's HT, possibly due to the wider caches, but also possibly because of the layout of the cores.

>>59238346
I think I read somewhere that AMD's SMT is coupled to some parts of the frontend including the caches that Intel isn't and that's where the performance is coming from.
And it's only their first generation of SMT, I'm really excited to see what Zen will look like when all kinks and stuff that got left out due to time constraints get included in the next gen.

>>59238385
Is the core gonna be upgraded every year or are we left waiting 2 years for Glofo/TSMC to get their 7nm functioning?

I mean if AMD doesn't upgrade their core every year then I don't know what to say, they did it with Bulldozer and that was pretty much on the company backburner after 2012.
But I haven't seen a roadmap about Zen+ so hence the skepticism.,

16 and 32 parts are gonna be really impressive, I could run a VM environment for my entire family with them, much better than buying them new hardware, plus I have full control and snapshots so no fixing fucking viruses and crap.

File: CB15 scaling.png (64KB, 960x540px) Image search: [Google]

64KB, 960x540px

cTDP caps the total power consumption to a certain value.
The power consumption will never be exceeded, no matter the workload or number of utilized cores. It works exactly like a rev limiter in engines.
The performance impact of limiting the power consumption will naturally depend on the number of utilized cores and the workload. Obviously at e.g. 30W you will be able to run a single core close to its maximum XFR ceiling, while the "n" core stress frequency will be more limited.
On Zeppelin the capped figure is the "Package Power" (PP), unlike with all of the previous designs (excl. Carrizo / Bristol Ridge). This means that all of the different domains (e.g. PCIe Phys, peripherals, etc) are included to this power limit, not just the CPU cores & northbridge like with designs such as Orochi (PD), Kaveri (SR), etc. It is truly a total package power limit.

Neat.

File: peak power.png (45KB, 960x540px) Image search: [Google]

45KB, 960x540px

Under 60w for a static 3.3ghz.
Accounting for uncore at that clock its about 6.25w per core to hit 3.3ghz.

Zen on 14nm LPP shines at low power like nothing else.

File: Win10 SMT.png (70KB, 794x447px) Image search: [Google]

70KB, 794x447px

Well well well. This is certainly interesting.

File: HC chart.png (575KB, 2450x1202px) Image search: [Google]

575KB, 2450x1202px

>>59239633
If Microsoft patches this issue in Win10 then theres a good chance performance might increase across the board.
The 1800X will be even better positioned against the i7 6900k.
The 1700's value prospect is quite something.

>>59239396
How much do 8 Broadwell cores use under 3.3?

>>59239396
If someone thought this wasn't a mobile/server first design after seeing this then further words would be futile.

>>59239914
Looking at the Broadwell Xeon E7s and the Xeon D line, it appears that a Broadwell core needs 4.6-5w to hit 2.4ghz and sustain it.

>>59239396
Did he test idle power anywhere?

>>59240163
TheStilt didn't, though TomsHardware did somewhat.
They didn't look at the long idle suspended state, but looked at the draw just sitting at the desktop.
http://www.tomshardware.com/reviews/amd-ryzen-7-1800x-cpu,4951-11.html

Under 15w sitting on the Win10 desktop.

Now that I look at it, Zen is AMD's Broadwell in the desktop.

>>59237203
>Zen can't overclock on the top end SKUs
yet
wait for BIOS updates.

>>59240551
This isn't going to change. The voltage scaling is a characteristic of the process Vt.

>>59240105
That sounds like a 20-25% efficiency deficit compared to Zen and that's not including the platform power.

How much is Skylake better than Broadwell?

>>59240904
I haven't bothered to look up Skylake, but TomsHardware has a decent look at Kaby Lake.
http://www.tomshardware.com/reviews/intel-kaby-lake-core-i7-7700k-i7-7700-i5-7600k-i5-7600,4870.html

The locked i7 7700 has a 3.6ghz base clock, and under a heavy FPU load it pulled 12.5w per core. I'd like to see a similar review for one of their mobile chips to look at power scaling with lower TDP SKUs, but I haven't found one, and I don't feel like buying or borrowing one to test myself.

>>59240904
Best take a look at mobile 15W broadwell and skylake chips, they all pretty much use similar power and the only generational difference is IPC and clockspeed.

>>59237203
I wonder if they'll use the same process for APUs.

>>59241140
Of course they will, but the scaling should be slightly better due to process tweaks, APUs won't use the zeppelin die.

File: RR.png (25KB, 657x142px) Image search: [Google]

25KB, 657x142px

>>59241170
>>59241140

>>59241208
Does Glofo have some kind of lower power process?
I thought LPP was their low power one.

>>59241261
Maybe Samsung has something improved, they've been using LPP for a while now.

>>59241261
Well, they got IBM's 14nm HP SOI process.

Also, 14nm LPP isn't just one process. There are multiple density libraries (which do influence voltage and frequency scaling a lot) available.
Zen is speculated to use one of the "higher mid-range" libraries.

>>59241261
Samsung has different variations of their 14nm process, including a higher clocking variant 14nm LPU.
Its also entirely possible that Raven Ridge APUs could be TSMC 16nm FF+. Decreasing load on Global Foundries Fab8 may be desirable given the high demand for Zen based parts and upcoming Vega GPUs.

AMD has claimed that mobile Raven Ridge will scale down to 4w TDP, and you don't get that just by shutting off cores and CU. A lot of it has to come from process.

>>59241372
That's even lower than Core M, are they trying something funny in the tablet market?

>>59241459
Its possible, but I'd say its more likely they'll have variable TDP chips for the Ultrabook market.

>>59241661
>>59241459
Even if it's AMD I won't buy a 4W TDP/8W "SDP" fanless laptop, give me my 15W one and we're good.

> The base-clock (BCLK)

>Overclocking the base clock (BCLK) on AM4 platform is possible, however generally not recommended. This is due to its frequency relations with other interfaces, such as the PCIe. Unlike with Intel's more recent CPUs, there is no asynchronous mode (straps / gears) available, which would allow stepping down the PCIe frequency at certain intervals. The PCIe frequency relation is fixed and therefore it increases at the same rate with the BCLK. Gen. 3 operation can generally be sustained up to ~107MHz frequency and higher speeds will usually require forcing the links to either Gen. 2 or to Gen. 1 modes.

>Unstable PCIe can cause various issues, such as system crashes, data corruption (M.2 SSDs), graphical artifacts and various kinds of other undefined behavior.

hmm...
this plus the IOMMU thing don't seem too good, IMO

>>59242253
Thats pretty standard. Until intel desynchronized everything tied to the NB it was the case on all their chips as well. Pushing base clocks too high would break PCI-E/USB/SATA functionality.
Ryzen doesn't have much OC headroom so theres no much point in altering the base clock.

>>59242300
aha
haven't bought CPUs in a while, the APU in my laptop overclocks greatly, so I'm surprised these ones can't do much... guess we are really paying the price of hitting very high efficiencies