>Intel fucked up 10nm and delayed it and put Kaby Lake in

>>55953361
B-but 16 and 32 core Zen will save us!

>>55953399
Both are server cpus and will probably be priced out the ass. Not to mention they'll be clocked low as servers normally are.

I can bet you it'll be priced similar to current Opterons so expect the 16 core to be near $800.

>>55953461
I bet all my money that they make some crazy FX9590 shit again. 16 cores, 4GHz, 200W TDP, need MOBO from fucking titanium to run. Priced at 200-250

File: amd_stratedgy.png (224KB, 778x960px) Image search: [Google]

224KB, 778x960px

>>55953399

Yep, it's fucked. Intel has moved forward and AMD can't catch up, Intel has no competition, which is bad for everyone else. Silicon is on its physical limits, can't keep shrinking the die forever.

>>55953361
Zen isn't a chip, its a core architecture.
Summit Ridge competes against Haswell-E and mid range Broadwell-E. They're not mainstream desktop chips.

>>55953556
Socket AM4 doesn't support quad channel memory, there will be no MCM chips on the socket. You're not getting any Opterons pushed onto the consumer market.

The FX 9590 wasn't "some crazy shit" they were just garbage higher leakage binnings of the standard FX 8350 that clocked higher. It simply was a matter of recouping losses since they weren't suited to be FX 8350s or 8320s.

>>55953944
>which is bad for everyone
>implying

>>55953877
It's depressing how accurate this is

>>55953361
Nothing has being released from zen, but you're already crying.

>>55953987
It is. Intel can price CPU's insanely high, and who's going to stop them? The other option is AMD which is stuck in 2008 with their CPU's. This is good for Intel because it increases profits but bad for the consumers.

File: 1443927645011.gif (2MB, 448x252px) Image search: [Google]

2MB, 448x252px

>>55953877
This hasn't been relevant since AMD learned the hard way that it can't release the Pentium 4 without running into the heat wall itself. I hope they fired every one involved in that shitchip.

File: 1391088349.jpg (141KB, 600x300px) Image search: [Google]

141KB, 600x300px

>>55953944
>Silicon is on its physical limits, can't keep shrinking the die forever.

They need to switch to "extreme UV" machines.
They are problematic, but they are close to being used in production now.

With EUV they can go at least to 7nm, and likely smaller.

>>55954095
I just tried to read about this on Wikipedia and I have no fucking idea what I'm reading.

Can you explain it in simple terms?

0nm when

>>55954188
The light source used in photolithography determines the minimum feature size, the physical wave length of the light is a limiting factor.
EUV is needed to produce smaller front end of line features and further facilitate standard CMOS scaling.

Incredibly simple.

>>55954188
>>55954209

What he said.

But the problem is extreme UV light cannot pass through glass or even air.
So instead of using lenses (like they did before), they have to use mirrors inside a vacuum chamber.
- that's what my picture shows.

And becasue mirrors are quite inefficient you need a very powerful light source.
Which in turn causes problems with heat and pollution from the source itself (which is a plasma).
So engineering nightmare....but they got it pretty much figured out and just need to tweak it to boost efficiency now.

btw: there is just one company that can make these machines, ASML, and all chip makers use them so don't expect any one chip maker to get very far ahead of the competition.

File: RTEmagicC_1kbMemory_Feynman_HR.jpg.jpg (126KB, 457x600px) Image search: [Google]

126KB, 457x600px

>>55954197
Smallest memory is already less than 1nm per bit.
These are individual chlorine atoms that are moved slightly to encode a "0" or a "1".

>>55954039
He was implying it's bad for everyone except Intel.

>>55954348
Intel is still investing in both EUV and immersion lithography. They're not sure which one will come out ahead so they're paying for both.

>>55954484
10nm chips can be made on both immersion and euv.
Anything smaller and you really need euv.

But immersion will still be used for less critical layers.
So Intel, and all their competitors, will still be buying the good old immersion machines.

>>55953361
glad i got my 6600K already

File: 0.jpg (48KB, 598x356px) Image search: [Google]

48KB, 598x356px

>human beings have turned sand and metal into devices smaller than a thumbnail

>these processors have components that are the size of tens of atoms

>processors that operate at billions of cycles per second

>often with 4 or more cores

>all for the cost of a few hundred dollars

and people still bitch that they're not enough. as though the computer engineers that make these miracles happen are just sitting on their asses with a finger in their nose.

there's some sort of impression that further and further miniaturization of transistors and continued logarithmic growth of computing power is some sort of birthright

i never thought i'd say this phrase in an un-ironic way, but: check your fucking privilege

>>55954095
7 nm has been canceled, haven't you heard? It'll be more economical to increase density by growing ICs vertically.

http://spectrum.ieee.org/tech-talk/computing/hardware/transistors-will-stop-shrinking-in-2021-moores-law-roadmap-predicts

>>55955166
They're talking about the isolated gate length itself, and they're intentionally omitting a ton of detail. Its a typical clickbaity article, even if they did try to be slightly technical. In a completely insulated device electron tunneling doesn't happen, SiGe channels and "QWFET" style devices facilitate gate lengths below 10nm. There are transistor topologies that lend themselves to shorter gate lengths as well.

http://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=2426&context=nanopub

Gate length by itself is one of the least important aspects of area scaling, its just a central metric. The back end, and the distance between the source/drain wells are vital. You can have a 10nm wide gate, but a full transistor including wells be 50nm or wider. There is far more to area scaling than that single isolated metric.