Threadripper PCIe lanes

>>61846564
>Can we
no

>>61846564
I approve this thread, this is not a "gaymers BTFO >>>/pcbg/"-tier.

>>61846564
AYYMD BTFO.

And no, it would be retarded if the chipset had its lanes connected to two different dies as any chipset operation would incur that penalty. As to what lanes they're hooked up, ask the motherboard manufacturer, or probe it with a multimeter and check the pin out which should be somewhere in a datasheet, if you want to be autistic and setup process affinity.

>>61846784
>it would be retarded if the chipset had its lanes connected to two different dies as any chipset operation would incur that penalty.
That's wrong. Spreading chipset lanes to both dies actually makes sense.
You don't need all 4 lanes just to access it anyway. Just 2 are enough.
This way you have constant latency on chipset operations.

But if you use 4 lanes from the single die, half of the times, you will have much higher latency.

>>61846845
nigger look at any 2 socket system. CPU0 always has the chipset attached if there is only one.

>>61846865
Threadripper is not a real 2 socket system.

>>61846892
It may as well be. Its two died glued to a interposer with the same latency issues.

File: AMD-X399-Chipset-740x682.jpg (131KB, 740x682px) Image search: [Google]

131KB, 740x682px

Before you start a stupid question thread, spend 2 mins googling.

>>61846845
>>61846892
see >>61846914 and stay btfo

File: ancient.png (291KB, 600x399px) Image search: [Google]

291KB, 600x399px

>>61846564
>I heard you like high latencies
>so we glued 2 dies each with 2 ccx and made TR so you can have high latency while you already have high latency

It's attached to cpu0. But what worries me is that it only supports 8 separate pcie devices as standard without retimers. Which explains why every motherboard is 4gpu + 3nvme + pch. I was looking forward to a silly board whet even everything is bifurcated to 4x or 8x slots.