THANK YOU BASED INTEL
>based intel
Coffee Lake isn't compatible with Z270. A chipset change a year keeps the goyim in fear.
You forgot this, OP
>CFL-S DELAYED
Wow, a whole 24 lanes!
>>61713004
Are you stupid or retarded? It's launching soon in Q3 which is this quarter
Retarded person that can't even read the roadmap
>>61713025
That is actually bad .. they already rushed X299. Now they're rushing their mainstream platform, too? Can't wait to see meltdown temps and throttling VRMs for the everyday user.
>>61712987
>>61713004
>>61713020
DELETE THIS YOU STUPID GOY
>>61713025
Here's the previous slide. Definitely won't be launching this August
>>61713071
Again, are you stupid or retarded?
Intel is launching it Aug-Sep with Z370 chipset
The second launch will be in January at CES with the new Z390 chipset mobo
Fucking retards that parents put to school but don't read or understand roadmaps
>>61713116
Not slide OP but...z370-z390?
You mean a refresh of a refresh already refreshed?
Damn, intel is shurely fucking up. Still waiting to see if 6-8c CPU become mainstream so AMD 12-16c parts drop prices a bit.
>>61713004
what happened?
>>61712944
>chipset lanes
Lol
>>61713214
They got bitchslapped by the laws of physics and couldn't find a way around it.
>>61713004
So wait, they're launching Coffee Lake again in 2018 on Cannonlake mobos because Cannonlake isn't ready?
>>61713320
More like they had monopoly so they had no real reason to bother researching new production methods.
>>61713584
Wrong. They weren't developing new architectures. They were actually relying on their foundries and process nodes to carry all the weight. And then it didn't work out.
>>61713559
Only the stuff they didn't launch this Aug or Sept
Mostly the notebook -U SKUs, Cores, Pentiums, Celerons
>>61712944
>up to
>>61713320
Just bribe the laws of physics, goy
>>61712944
>thank you based Intel for limiting my PCIe lanes
You mong.
>>61712944
>No drivers for Windows 7 - 8.1 or Linux
no thank you
>>61712944
from changing a socket each year
now intel changes 2 each year!
we are going towards a system that mid low high will have its own socket
>>61712944
>24 chipset lanes
>All limited by < PCI-E x4 bandwidth of the DMI link
Really intel?
>rush SKylake X
>housefire temps and power consumption along with faulty mobos
>plan to rush Coffee Lake S
How fucking scared is Intel? Jesus Christ AMD released their first good CPU in over 6 years and Intel goes in full panic mode. What's hilarious is Coffee Lake has to be 95W, if it has heat problems people are going to blow up their sockets.
>>61712944
What, we have to thank them for ripping us off now?
>>61712944
>6core rushed housefire on mainstream socket
lmao
>>61713839
>bribe
Be very careful anon.
In land of free term "lobby" is much more appreciated.
>>61712944
Four fucking generations in the same year!
Intel is a disastre!
>>61715248
Last time I looked at a paper for the intel chipsets I think a lot of the lanes are shared multifunction things. So to get 24pcie you'd have to sacrifice most of the the usb and sata options. Which no one ever does.
On the otherhand x370 should have had 8x pcie3 on the chipset so there was the option for at least one expansion slot that could work at full speed. if the pch wasn't doing much else.
>>61716228
>On the otherhand x370 should have had 8x pcie3 on the chipset so there was the option for at least one expansion slot that could work at full speed. if the pch wasn't doing much else.
Would still be limited by the link speed to the CPU. Keep in mind both AMD and Intel at this point link their chipsets to the CPU through overglorified PCI-E x4 links. The chipset feeding 8 lanes is no good if they're bottlenecked by the link to the CPU.
>>61716283
My point was that the current 8x pcie2 on the x370 can't feed a pcie3 4x card in any fashion even if the rest of the pch is doing nothing, which isn't that unlikely when there are usb and nvme/sata directly attached to the cpu (not that I think any motherboard have direct attach sata)
>>61713071
2 CORE
LMAO 2 CORE
>>61716283
Doesnt seem much of an issue for TR with 64 lanes and EPYC with it's 128 lanes and it being an SoC
Okay now with crossfire/sli pretty much dead as a technology could you please explain why would I ever need more than 16 pcie lanes?
>>61716825
That's because they have an unholy fuckton of lanes direct to the CPU. The x4 link TR has to its chipset is only really used for peripherals and any sata drives linked to it that dont go direct to the CPU (which IIRC has onboard sata controllers due to it being a SOC). You'd really have to try and saturate it.
Ryzen and Intel's offerings though, due to their much reduced CPU lane count, have alot more hanging off the chipset, including NVME drives. Throw in a GPU on top of that and the x4 link to the CPU from the chipset will choke.
>>61713214
they didn't spun off their fabs when it was convenient to do so and didn't see mobile was gonna fuck them in the ass big time, both by direct competition with their atom line and indirectly by moving enormous volumes thanks to which glofo and tsmc managed to catch up process nodes
>>61712950
>selling dual cores in 2017
So their yields turned into pure undiluted shit thanks to some Brian management magic?
Hasn't it been 3 years since they started to fab on their current node? Did they decide to keep ridiculous framentation?
>>61719669
The dual cores are probably the pentiums/celerons still.
>>61713116
PRODUCTION window: Week 34 - 41. Let me spell that our for you - it means it will be in production in week 34 EARLIEST. Do you think it only takes one week from production to retail? Slide >>61713071 shows PRODUCT INTRODUCTION in August. That means they are going to miss that date. That means it is DELAYED. Please learn to read
>>61713214
>10nm 2016
haha