Reminder folks, microcode/firmware makes all the difference.

>higher is better

subjective opinion

What I think is happening here, AMD is tweaking their internal scheduler to keep as much work in a CCX as possible before hopping to another, EPYC is at its most powerful when a task can be split apart per 8MB slice of cache.

>>61488849
>tweaking their internal scheduler

the only "internal scheduling" on a CPU is tunable microcode decoding within a core and balancing resources between SMT threads differently.

everything else they control is outside the realm of scheduling, like mapping physical address spaces to caches differently or tuning IF bus behavior.

what you're talking about (high level task scheduling) is purely under OS control.

>>61488897
You meant to tell me CPUs aren't advanced enough to know if a certain thread the OS inefficiently scheduled to Y core is unwanted on Y core it can't move it to some other one?

Because bad thread scheduling is the bane of the EPYC design, you don't want a thread hounding for example core2 if something else is already happening on it.

>>61488805
Now that is an EPYC improvement (seewhutididthere)

>>61488805
cinebench on the updated microcode when? the 2S system was scoring like a turd before

File: 1497020071620.png (162KB, 633x900px) Image search: [Google]

162KB, 633x900px

>>61488805
NO IT'S NOT FAIR

>>61488835
I'm siding with Bill Gates on this one.